From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 92C863858D28; Thu, 4 May 2023 08:06:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 92C863858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683187566; bh=ckcV4Afm5R71QdRcOJNOM+l9Brlwragi4VhpRiu06Ek=; h=From:To:Subject:Date:In-Reply-To:References:From; b=VFvFVt7zWFH9scjwcYg6KUv5/is0SwCXTiyMOCmc6iS9KPG27SzKqDUs24b2RtDuV URgDzeC6OY4qp+3LL1qDdRizDu4cxoHFiyoJhiK3KLb7F7x2Thd8fwYlse6zA68Ghz kpSS8qeLZTItOQFcpvpBBR8ELXlN3hwGivSso+6U= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/109721] [14 Regression] predcom-2 started to fail on arc-elf after r14-391 Date: Thu, 04 May 2023 08:06:06 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: testsuite-fail X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rguenth at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109721 --- Comment #3 from Richard Biener --- Huh, we indeed vectorize count_averages (). But I have no idea how the offending rev should have changed this ... Ah. Before we had gcc.dg/tree-ssa/predcom-2.c:27:55: missed: not vectorized: relevant stmt = not supported: _9 =3D _8 & 65535; but now we let this slip through with gcc.dg/tree-ssa/predcom-2.c:26:17: note:=20 proceeding using word mode. but we do not actually use word_mode. Later veclower decomposes the bitwise vector and: - vect__9.38_33 =3D vect__8.37_31 & { 65535, 65535 }; + _26 =3D BIT_FIELD_REF ; + _19 =3D _26 & 65535; + _23 =3D BIT_FIELD_REF ; + _10 =3D _23 & 65535; + vect__9.38_33 =3D {_19, _10}; Btw, when writing the patch I noticed we let SImode AND through when target_support_p even though it isn't word_mode and I didn't want to change that but had to catch the case where SImode PLUS is supported (well, obviously...) but emulated vectors rely on it being word_mode. I'm going to amend this more. But maybe this arch is also missing bit operation vector support for some unknown reason.=