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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109725] [14 Regression] ICE: RTL check: expected code
 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
Date: Thu, 04 May 2023 04:27:34 +0000
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X-Bugzilla-Type: changed
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: build, ice-checking, ice-on-valid-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109725

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2023-05-04
             Status|UNCONFIRMED                 |NEW
   Target Milestone|---                         |14.0
     Ever confirmed|0                           |1
           Keywords|                            |ice-checking

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Yes this is bad coding:
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
  /* `~` does not take an operand so op will be null
     Check for before accessing op.
  */
  if (letter =3D=3D '~')
    {
      if (TARGET_64BIT)
        fputc('w', file);
      return;
    }
  machine_mode mode =3D GET_MODE (op);
  enum rtx_code code =3D GET_CODE (op);
  const enum memmodel model =3D memmodel_base (INTVAL (op));


model should only be defined where it is used rather than in the top.=