From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 2DCB33856DDA; Thu,  4 May 2023 19:30:27 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2DCB33856DDA
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1683228627;
	bh=e+l7WzleKu8+K9IPZsEUt1C/jSrZJjvgw0E2BbvwXA0=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=dd2jLo32l66cg7G7NGdvMMxEFyzGYS4WQPQY0dEIoqLQqfaJqtKAOCDhmldplfWwP
	 Cytqk/Qoxwq9MBl//ZunKh7O9mxA2eP6u18fAgKz9RFAkkB3M+pVN6xE/wX2WL98/U
	 U66KUUB1mXEpOhO6hRpAWc87WHu9YT73y+O8tKuc=
From: "janezz55 at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug libstdc++/109741] alignas(64) in
 libstdc++-v3/src/c++11/shared_ptr.cc
Date: Thu, 04 May 2023 19:30:26 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: libstdc++
X-Bugzilla-Version: 13.1.0
X-Bugzilla-Keywords: 
X-Bugzilla-Severity: normal
X-Bugzilla-Who: janezz55 at gmail dot com
X-Bugzilla-Status: NEW
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-109741-4-AKtvuWwx2c@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-109741-4@http.gcc.gnu.org/bugzilla/>
References: <bug-109741-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109741

--- Comment #13 from Janez Zemva <janezz55 at gmail dot com> ---
@Jonathan Wakely
I asked ChatGPT about this:

What is the most common size of a cache line?
The most common size of a cache line is 64 bytes. This size is used by most
modern CPUs because it strikes a balance between the amount of data that ca=
n be
stored in a cache line and the amount of overhead required to manage the ca=
che.
However, it's important to note that different CPUs and cache designs may u=
se
different cache line sizes based on their specific requirements and trade-o=
ffs
between performance and resource usage.

This means the "right" number is architecture-dependent and my proposals we=
re
not  wrong for every possible architecture.=