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Subject: [Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic
 VSETVL
Date: Sat, 06 May 2023 02:22:56 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109748

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:8421f279e9eb00a2342ee3630dcdaf735b734fe8

commit r14-538-g8421f279e9eb00a2342ee3630dcdaf735b734fe8
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri May 5 22:12:39 2023 +0800

    RISC-V: Fix incorrect demand info merge in local vsetvli optimization
[PR109748]

    This patch is fixing my recent optimization patch:
=20=20=20
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25=
260bbf

    In that patch, the new_info =3D parse_insn (i) is not correct.
    Since consider the following case:

    vsetvli a5,a4, e8,m1
    ..
    vsetvli zero,a5, e32, m4
    vle8.v
    vmacc.vv
    ...

    Since we have backward demand fusion in Phase 1, so the real demand of
"vle8.v" is e32, m4.
    However, if we use parse_insn (vle8.v) =3D e8, m1 which is not correct.

    So this patch we change new_info =3D new_info.parse_insn (i)
    into:

    vector_insn_info new_info =3D m_vector_manager->vector_insn_infos[i->ui=
d ()];

    So that, we can correctly optimize codes into:

    vsetvli a5,a4, e32, m4
    ..
    .. (vsetvli zero,a5, e32, m4 is removed)
    vle8.v
    vmacc.vv

    Since m_vector_manager->vector_insn_infos is the member variable of
pass_vsetvl class.
    We remove static void function "local_eliminate_vsetvl_insn", and make =
it
as the member function
    of pass_vsetvl class.

            PR target/109748

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
Remove it.
            (pass_vsetvl::local_eliminate_vsetvl_insn): New function.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/vsetvl/pr109748.c: New test.=