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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109807] [14 Regression] sse2-mmx-pmaddwd.c met ICE after
 commit r14-666-g608e7f3ab47 with march=cascadelake
Date: Thu, 11 May 2023 08:06:22 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109807

--- Comment #5 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to Haochen Jiang from comment #4)
> (In reply to Uro=C5=A1 Bizjak from comment #2)
> > (In reply to Haochen Jiang from comment #1)
> > > I further checked the reason, V2SI should never dropped into that fun=
ction
> > > because we have no pattern under V2SI.
> > >=20
> > > I suppose it is because -march=3Dcascadelake will open SSE4.1, with t=
he new
> > > pattern, it wrongly dropped into that.
> > >=20
> > > -m32 will not ICE since TARGET_MMX_WITH_SSE need 64 bit and won't ena=
ble the
> > > new pattern.
> >=20
> > V2SI mul was introduced in r14-493 (AKA partial fix for PR109690).
>=20
> I see. So we might need to add cost for that right?

Adding "case V2SImode:" above "case V4SImode:" in ix86_widen_mult_cost will=
 fix
this issue. Probably V4HImode is also needed above V8HImode, we have had a
mulv4hi3 pattern for some time now.=