From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 82E473858C50; Mon, 22 May 2023 13:01:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 82E473858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684760512; bh=Yv92oisNGiZQkxCGtl4DFPipBEm7VbZ8o3zGljaYJO0=; h=From:To:Subject:Date:In-Reply-To:References:From; b=T+XmN8FLrY76quBhvOMYZ3rScb2i7Apia3TJD2Ieg1eoOsCTD5dz3l415p74uTGyL DeDyRltDkSW0VnlANhgqUnSe+1mAsWmyGcS56DGwrrL4hHOqjtz3yGUghr4ruDH7Er Cx+2NWo2SwSwzeSIdQgrk6SQy00QYDI+6QHDODkU= From: "rsandifo at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109855] [14 Regression] ICE: in curr_insn_transform, at lra-constraints.cc:4231 unable to generate reloads for {aarch64_mlav4hi_vec_concatz_le} at -O1 Date: Mon, 22 May 2023 13:01:52 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rsandifo at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109855 --- Comment #3 from rsandifo at gcc dot gnu.org --- Looking at the mddump file, the output predicate and constraint seem to have gone AWOL: ;; /home/ricsan01/gnu/src/gcc/gcc/config/aarch64/aarch64-simd.md: 1554 (define_insn ("aarch64_mlav4hi_vec_concatz_le") [ (set (match_operand:V8HI 0 ("") ("")) (vec_concat:V8HI (plus:V4HI (mult:V4HI (match_operand:V4HI 2 ("register_operand") ("w")) (match_operand:V4HI 3 ("register_operand") ("w"))) (match_operand:V4HI 1 ("register_operand") ("0"))) (match_operand:V4HI 4 ("aarch64_simd_or_scalar_imm_zero") ("")))) ] ("(!BYTES_BIG_ENDIAN) && (TARGET_SIMD)") ("mla\t%0.4h, %2.4h, %3.4h") [ (set_attr ("type") ("neon_mla_h")) (set_attr ("add_vec_concat_subst_le") ("no")) ])=