From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 755323858418; Tue, 23 May 2023 10:09:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 755323858418 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684836599; bh=VhcLQUKVazF/zRhsrHorJwyVTxtEEKv7h2pZe+8m+3U=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Sltl3VsNKMgpGdjlg8iz+PKhjoMOtg3VRp0jM61D51UdwJk1ZsJUimy1Pe5HJgMvt CgYNDHfTMu9Els1VDkmIVZsIANR47ue+2BkMSek07aU42zTrELHNAuttJmBWGhfsOh rxiJHn+MZk/rVA49Xe6lseslpwSIBQS4Hv3El0Wg= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109855] [14 Regression] ICE: in curr_insn_transform, at lra-constraints.cc:4231 unable to generate reloads for {aarch64_mlav4hi_vec_concatz_le} at -O1 Date: Tue, 23 May 2023 10:09:58 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: ktkachov at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109855 --- Comment #8 from CVS Commits --- The master branch has been updated by Kyrylo Tkachov : https://gcc.gnu.org/g:75d1eff5933fc0d853af730627218f182612b561 commit r14-1128-g75d1eff5933fc0d853af730627218f182612b561 Author: Kyrylo Tkachov Date: Tue May 23 11:09:08 2023 +0100 aarch64: PR target/109855 Add predicate and constraints to define_subst= in aarch64-simd.md In this PR we ICE because the substituted pattern for mla "lost" its predicate and constraint for operand 0 because the define_subst template: [(set (match_operand: 0) (vec_concat: (match_dup 1) (match_operand:VDZ 2 "aarch64_simd_or_scalar_imm_zero")))]) Uses match_operand instead of match_dup for operand 0. We can't use match_dup 0 for it because we need to specify the widened mode. The problem is fixed by adding a "register_operand" predicate and "=3Dw" constraint to the match_operand. This makes sense conceptually too as the transformation we're targeting only applies to instructions that write a "w" register. With this change the mddump pattern that ICEs goes from: (define_insn ("aarch64_mlav4hi_vec_concatz_le") [ (set (match_operand:V8HI 0 ("") ("")) <<------ Missing constrai= nt! (vec_concat:V8HI (plus:V4HI (mult:V4HI (match_operand:V4HI 2 ("register_operand") ("w")) (match_operand:V4HI 3 ("register_operand") ("w"= ))) (match_operand:V4HI 1 ("register_operand") ("0"))) (match_operand:V4HI 4 ("aarch64_simd_or_scalar_imm_zero= ") ("")))) ] ("(!BYTES_BIG_ENDIAN) && (TARGET_SIMD)") ("mla\t%0.4h, %2.4h, %3.= 4h") to the proper: (define_insn ("aarch64_mlav4hi_vec_concatz_le") [ (set (match_operand:V8HI 0 ("register_operand") ("=3Dw")) <<---= ----- Constraint in the right place (vec_concat:V8HI (plus:V4HI (mult:V4HI (match_operand:V4HI 2 ("register_operand") ("w")) (match_operand:V4HI 3 ("register_operand") ("w"= ))) (match_operand:V4HI 1 ("register_operand") ("0"))) (match_operand:V4HI 4 ("aarch64_simd_or_scalar_imm_zero= ") ("")))) ] ("(!BYTES_BIG_ENDIAN) && (TARGET_SIMD)") ("mla\t%0.4h, %2.4h, %3.= 4h") This seems to do the right thing for multi-alternative patterns as well, the annotated pattern for aarch64_cmltv8qi is: (define_insn ("aarch64_cmltv8qi") [ (set (match_operand:V8QI 0 ("register_operand") ("=3Dw,w")) (neg:V8QI (lt:V8QI (match_operand:V8QI 1 ("register_operand= ") ("w,w")) (match_operand:V8QI 2 ("aarch64_simd_reg_or_zero") ("w,ZDz"))))) ] whereas the substituted version now looks like: (define_insn ("aarch64_cmltv8qi_vec_concatz_le") [ (set (match_operand:V16QI 0 ("register_operand") ("=3Dw,w")) (vec_concat:V16QI (neg:V8QI (lt:V8QI (match_operand:V8QI 1 ("register_operand") ("w,w")) (match_operand:V8QI 2 ("aarch64_simd_reg_or_zer= o") ("w,ZDz")))) (match_operand:V8QI 3 ("aarch64_simd_or_scalar_imm_zero= ") ("")))) ] Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: PR target/109855 * config/aarch64/aarch64-simd.md (add_vec_concat_subst_le): Add predicate and constraint for operand 0. (add_vec_concat_subst_be): Likewise. gcc/testsuite/ChangeLog: PR target/109855 * gcc.target/aarch64/pr109855.c: New test.=