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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/109907] Missed optimization for bit extraction (uses
 shift instead of single bit-test)
Date: Sun, 21 May 2023 05:15:59 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109907

--- Comment #15 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
So there is another way of fixing this. take:
Trying 6 -> 12:
    6: r49:SI=3Dr50:SI>>0x1f
      REG_DEAD r50:SI
   12: r24:QI=3Dr49:SI#0&0x1
      REG_DEAD r49:SI
Failed to match this instruction:
(set (reg/i:QI 24 r24)
    (neg:QI (subreg:QI (ashiftrt:SI (reg:SI 50)
                (const_int 31 [0x1f])) 0)))

It is correct but maybe the subreg should combine with the shift and change=
 it
just (lshiftrt:QI (subreg:QI (reg:SI 50)) (const_int 7)) . Once combine does
that, then maybe that could match ...


What is interesting is subreg1 does the splitting for HI mode .

Maybe Roger could look improving that since he was touching it recently for=
 avr
IIRC.=