From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 297FB385841E; Sun, 11 Jun 2023 09:22:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 297FB385841E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686475363; bh=ErdZ+olFv3HVA2Wca4ZDsSdtl463cxiUXje6sfaNgzM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Kodt5aLyff1q6jJlUvN4y1EunzGnBo/AyfoiXswGXivGng1ezJztI9nV8ESQI1eEv kZVZdWAtKF8aTpVwtmWd6UcqXhUrUNIZNAD3EM4xPHw8YaFUcSAJuZEU9niRKwtcyo DRvlCsBtMQXOrL7WJx+Wr944Sp661JRjZMqE1b08= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/109907] Missed optimization for bit extraction (uses shift instead of single bit-test) Date: Sun, 11 Jun 2023 09:22:40 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109907 --- Comment #30 from CVS Commits --- The master branch has been updated by Georg-Johann Lay : https://gcc.gnu.org/g:20643513b8dd34c07f2b0fccf119153a30735f66 commit r14-1694-g20643513b8dd34c07f2b0fccf119153a30735f66 Author: Georg-Johann Lay Date: Sat Jun 10 23:21:13 2023 +0200 target/19907: Overhaul bit extractions. o Logical right shift that shifts the MSB to position 0 can be performe= d in such a way that the input operand constraint can be relaxed from "0" = to "r". This results in less register pressure. Moreover, no scratch registe= r is required in that case. o The deprecated "extzv" pattern is replaced by "extzv" that allo= ws inputs of scalar integer modes of different sizes (1 up to 4 bytes). o Existing patterns are adjusted to the more generic "extzv" patt= ern. Some patterns are added as the middle-end has been reworked to spot more bit-extraction opportunities. o A C function is used to print the asm for bit extractions, which is m= ore convenient for complex output logic. The generated code is still not optimal because RTL optimizers might st= ill prefer arithmetic like shift over bit-extractions. For test cases see also PR36884 and PR55181. gcc/ PR target/109907 * config/avr/avr.md (adjust_len) [extr, extr_not]: New elements. (MSB, SIZE): New mode attributes. (any_shift): New code iterator. (*lshr3_split, *lshr3, lshr3) (*lshr3_const_split): Add constraint alternative for the case of shift-offset =3D MSB. Ditch "length" attribute. (extzv, *extzv..subreg, *extzv.xor) (*extzv.ge, *neg.ashiftrt.msb, *extzv.io.lsr7): New. * config/avr/constraints.md (C15, C23, C31, Yil): New * config/avr/predicates.md (reg_or_low_io_operand) (const7_operand, reg_or_low_io_operand) (const15_operand, const_0_to_15_operand) (const23_operand, const_0_to_23_operand) (const31_operand, const_0_to_31_operand): New. * config/avr/avr-protos.h (avr_out_extr, avr_out_extr_not): New. * config/avr/avr.cc (avr_out_extr, avr_out_extr_not): New funcs. (lshrqi3_out, lshrhi3_out, lshrpsi3_out, lshrsi3_out): Adjust MSB case to new insn constraint "r" for operands[1]. (avr_adjust_insn_length) [ADJUST_LEN_EXTR_NOT, ADJUST_LEN_EXTR]: Handle these cases. (avr_rtx_costs_1): Adjust cost for a new pattern. gcc/testsuite/ PR target/109907 * gcc.target/avr/pr109907.c: New test. * gcc.target/avr/torture/pr109907-1.c: New test. * gcc.target/avr/torture/pr109907-2.c: New test.=