From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 865D23858D20; Sun, 21 May 2023 09:09:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 865D23858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684660191; bh=KmF7ISRcJKmFRWXCJAbv2XX5nOKhaA4QEmrP/xKhy7A=; h=From:To:Subject:Date:In-Reply-To:References:From; b=bwS+txTr4dXkexZ3wRRMyJnPyL4fQPkRHDaSdSWs0ae5SMQNlYjhB7V+oHI4mVuFY 8E04yE2WBsulbfs6KXmFVb9+qZRqWsmaRKAqIfio0LHmNJpqWnn77N/h6OwqMhGyFV fcPGhB21lXIzVjorKPhhtZg88DkzeZWrq7lWWsm0= From: "gjl at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/109907] Missed optimization for bit extraction (uses shift instead of single bit-test) Date: Sun, 21 May 2023 09:09:49 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: gjl at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: attachments.created Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109907 --- Comment #17 from Georg-Johann Lay --- Created attachment 55129 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D55129&action=3Dedit Patch for AVR backend: combine patterns, "extzv", test case For now I have the attaches patch that resolves all cases of the included test-case. Iknow that the maintainers are not very fond of such combine patterns though... Provide more patterns to improve extracting (negated) single bits. Deprecated insn "extzv" is replaced by "extzv". The patterns now also allow lower I/O memory because both the insns and the instructions for I/O like SBIC/SBIS and the ones for REGs like SBRC/SBRS. Even in the presence of "extzv" there is no canonical form for single bit extractions, even less for extracting the insersed bit. So more than one mathod is provided. gcc/ PR target/109907 * config/avr/avr-protos.h (avr_out_extr, avr_out_extr_not): New pro= tos. * config/avr/avr.cc (avr_out_extr, avr_out_extr_not): New functions. (avr_adjust_insn_length) [ADJUST_LEN_EXTR_NOT, ADJUST_LEN_EXTR]: Handle cases. * config/avr/avr.md (adjust_len) [extr, extr_not]: Add to define_at= tr. (extzv): Turn into extzv. (MSB): New mode attribute. (*extzv_split, *extzv): Allow lower I/O addresses in operand 1. Unify constraints to a single case, as avr_out_extr() will now handle the alternatives. (*extzv.not_split, *extzv_not): New insn and its post-reload split. (*extzv.subreg., *extzv.neg.subreg-msb., *extzv.g= e): New insns and post-reload splits. (*extzv.xor, *extzv.io.lsr): New insns and pre-reload split. * config/avr/constraints.md (Yil): New constraint for reg or low I/= O. * config/avr/predicates.md (reg_or_low_io_operand, const7_operand) (const15_operand, const23_operand, const31_operand) (const_0_to_7_operand, const_0_to_15_operand, const_0_to_23_operand) (const_0_to_31_operand): New predicates. gcc/testsuite/ PR target/109907 * gcc.target/avr/pr109907.c: New test. =