From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7796E3858C30; Thu, 1 Jun 2023 01:40:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7796E3858C30 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685583649; bh=N3ceSon8l6N/nRgfa7owbfk2OJiAvrxijdmLjHOOwuM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=kV0MMq4MbmswKhCyQFBWzwcBm5nbwIQ62/QxIx+dMqOsGV/mDOxYtNdzC9A3Sp90t VbbFK09bLO4XP2+GGwNqqUHYZpk8IBHQ95RzemKCDubQpiB9EdGkly4YUOxm5hPina DeIkI8MoGghSP2gLU+evoHI0R1BIiOCrgZDKT0oE= From: "Simon.Richter at hogyros dot de" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/109930] transform atomic exchange to unconditional store when old value is unused? Date: Thu, 01 Jun 2023 01:40:48 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 13.1.1 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: Simon.Richter at hogyros dot de X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109930 --- Comment #5 from Simon Richter --- > Btw if you know the old state then there is presumably no concurrent acce= ss here and so you don't need atomic, let alone sequential consistency. I know it in some, but not all cases. Basically, what I do is auto old_x =3D x.load(); retry: switch(old_x) { case 1: if(!x.compare_exchange_weak(old_x, 2)) goto retry; stop_timer(); old_x =3D x.exchange(4); assert(old_x =3D=3D 2); break; case 2: // we must have preempted another instance of this function // do nothing break; case 3: // handle timeout ... break; case 4: // handle operation complete ... } This is in code for timeout handling in a realtime system, the timer interr= upt can preempt this. State 1 is "operation in progress", state 2 is "operation finished", state 3 is "operation timed out", and state 4 is "operation fini= shed and timer stopped", and the timer interrupt will try to switch from 1 to 3. The transient state 2 then solves the race between the timer expiring and stopping the timer (which is asynchronous because the interrupt controller = has a few cycles delay). So the switch from state 2 to state 4 has release semantics.=