From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 164693858D39; Fri, 26 May 2023 02:42:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 164693858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685068930; bh=sFbUWAcqx22lrLa8AVnagQWDzZwuQfrwBFjtCzPUw5U=; h=From:To:Subject:Date:From; b=crEPCM7oBLFj5Kp0Ssx9oxBkHci1Mvy3225tJDZp2vSRvMMHbuGOsB8N6pgengsgK 8OzBfNu709FAojcspSFS2hU0ksGHxu1+JUJGvPGrsqyGHW7EJ+CHHHgGB0asq+cJQj Keum+tsNTEA7Cx2qU1JFUtY86V1fwi6b70lXBIrw= From: "pan2.li at intel dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/109974] New: RISCV: RVV VSETVL Pass ICE in SLP auto-vectorization Date: Fri, 26 May 2023 02:42:09 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: pan2.li at intel dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone attachments.created Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D109974 Bug ID: 109974 Summary: RISCV: RVV VSETVL Pass ICE in SLP auto-vectorization Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pan2.li at intel dot com Target Milestone: --- Created attachment 55160 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D55160&action=3Dedit Reproduce source file Given the below example code with build option " -march=3Drv64gcv_zbb -O3 --param=3Driscv-autovec-preference=3Dfixed-vlmax". #include void __attribute__((noinline, noclone)) func (int8_t *__restrict x, int64_t *__restrict y, int n) { for (int i =3D 0, j =3D 0; i < n; i++, j +=3D2 ) { x[i + 0] +=3D 1; y[j + 0] +=3D 1; y[j + 1] +=3D 2; } } It will trigger one ICE during RTL pass: vsetvl. .file "test.c" .option nopic .attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zbb1p0_zve32f1= p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" .attribute unaligned_access, 0 .attribute stack_align, 16 .text during RTL pass: vsetvl test.c: In function =E2=80=98func=E2=80=99: test.c:12:1: internal compiler error: in source_equal_p, at config/riscv/riscv-vsetvl.cc:1141 12 | } | ^ 0x1cd6902 source_equal_p =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:1141 0x1cd7c59 riscv_vector::avl_info::single_source_equal_p(riscv_vector::avl_i= nfo const&) const =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:1658 0x1cd7f01 riscv_vector::avl_info::operator=3D=3D(riscv_vector::avl_info con= st&) const =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:1722 0x1cd8fe0 riscv_vector::vector_insn_info::compatible_avl_p(riscv_vector::vl_vtype_info const&) const =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:2010 0x1cd6ce4 incompatible_avl_p =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:1199 0x1ce453b riscv_vector::demands_cond::dual_incompatible_p(riscv_vector::vector_insn_i= nfo const&, riscv_vector::vector_insn_info const&) const =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.h:491 0x1cd8e36 riscv_vector::vector_insn_info::compatible_p(riscv_vector::vector_insn_info const&) const =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:1983 0x1cdbf13 pass_vsetvl::compute_local_backward_infos(rtl_ssa::bb_info const*) =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:2819 0x1ce188b pass_vsetvl::lazy_vsetvl() =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:4542 0x1ce1b40 pass_vsetvl::execute(function*) =20=20=20=20=20=20=20 /home/pli/repos/gcc/reference/riscv-gnu-toolchain/gcc/__BUILD_RISC-V/../gcc= /config/riscv/riscv-vsetvl.cc:4601 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See for instructions.=