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From: "d_vampile at 163 dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110024] [Bug] 5% performance drop on important benchmark after r260951.
Date: Mon, 29 May 2023 15:19:20 +0000	[thread overview]
Message-ID: <bug-110024-4-wf4fI2V8Vj@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110024-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110024

--- Comment #3 from d_vampile <d_vampile at 163 dot com> ---
(In reply to Andrew Pinski from comment #2)
> Which core is showing the difference here?
> Because some cores I know of, loading/storing using the FP registers is
> actually one cycle slower than using GPRs.
Yes, you're right; This submission is due to my careless post wrong assembly
code location; The performance is better when the X0 register is used before
the modification. The question, however, is why this modification causes the
register to select D0 and performance degradation. In addition, I will continue
to follow up in the new submission, look forward to your reply.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110026

      parent reply	other threads:[~2023-05-29 15:19 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-29 14:42 [Bug target/110024] New: " d_vampile at 163 dot com
2023-05-29 14:46 ` [Bug target/110024] " d_vampile at 163 dot com
2023-05-29 14:48 ` pinskia at gcc dot gnu.org
2023-05-29 15:09 ` d_vampile at 163 dot com
2023-05-29 15:19 ` d_vampile at 163 dot com [this message]

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