[Bug target/110027] [11/12/13/14 regression] Misaligned vector store on detect_stack_use_after_return

["liuhongt at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110027

--- Comment #12 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
(In reply to Sam James from comment #11)
> Calling it a 11..14 regression as we know 14 is bad and 7.5 is OK, but I
> can't test 11/12 on an avx512 machine right now.

I can't reproduce that with 11/12, but with gcc13 for the case in PR114276.

It looks like the codegen is already wrong in .expand, the offensive part is
mentioned in #c0

>Now, if `__asan_option_detect_stack_use_after_return` is 0, the variable at >%rcx-128 is correctly aligned to 64. However, if it is 1, __asan_stack_malloc_1 >returns something aligned to 64 << 1 (as per https://github.com/gcc->mirror/gcc/blob/master/gcc/asan.cc#L1917) and adding 160 results in %rcx-128 >being only aligned to 32. And thus the segfault.


;; Function foo (_Z3foov, funcdef_no=14, decl_uid=3962, cgraph_uid=10,
symbol_order=9)

(note 1 0 37 NOTE_INSN_DELETED)
;; basic block 2, loop depth 0, maybe hot
;;  prev block 0, next block 3, flags: (NEW, REACHABLE, RTL, MODIFIED)
;;  pred:       ENTRY (FALLTHRU)
(note 37 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 37 3 2 (parallel [
            (set (reg:DI 105)
                (plus:DI (reg/f:DI 19 frame)
                    (const_int -160 [0xffffffffffffff60])))
            (clobber (reg:CC 17 flags))
        ]) "test1.cc":7:12 247 {*adddi_1}
     (nil))
(insn 3 2 4 2 (set (reg:DI 106)
        (reg:DI 105)) "test1.cc":7:12 82 {*movdi_internal}
     (nil))
(insn 4 3 5 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (mem/c:SI (symbol_ref:DI
("__asan_option_detect_stack_use_after_return") [flags 0x40]  <var_decl
0x7f8d26f37900 __asan_option_detect_stack_use_after_return>) [4
__asan_option_detect_stack_use_after_return+0 S4 A32])
            (const_int 0 [0]))) "test1.cc":7:12 7 {*cmpsi_ccno_1}
     (nil))
(jump_insn 5 4 93 2 (set (pc)
        (if_then_else (eq (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref 11)
            (pc))) "test1.cc":7:12 995 {*jcc}
     (nil)
 -> 11)
;;  succ:       5
;;              3 (FALLTHRU)

;; basic block 3, loop depth 0, maybe hot
;;  prev block 2, next block 4, flags: (NEW, REACHABLE, RTL, MODIFIED)
;;  pred:       2 (FALLTHRU)
(note 93 5 6 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 6 93 7 3 (set (reg:DI 5 di)
        (const_int 128 [0x80])) "test1.cc":7:12 82 {*movdi_internal}
     (nil))
(call_insn 7 6 8 3 (set (reg:DI 0 ax)
        (call (mem:QI (symbol_ref:DI ("__asan_stack_malloc_1") [flags 0x41] 
<function_decl 0x7f8d26fa2400 __asan_stack_malloc_1>) [0  S1 A8])
            (const_int 0 [0]))) "test1.cc":7:12 1013 {*call_value}
     (expr_list:REG_EH_REGION (const_int -2147483648 [0xffffffff80000000])
        (nil))
    (expr_list (use (reg:DI 5 di))
        (nil)))
(insn 8 7 9 3 (set (reg:CCZ 17 flags)
        (compare:CCZ (reg:DI 0 ax)
            (const_int 0 [0]))) "test1.cc":7:12 8 {*cmpdi_ccno_1}
     (nil))
(jump_insn 9 8 94 3 (set (pc)
        (if_then_else (eq (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref 11)
            (pc))) "test1.cc":7:12 995 {*jcc}
     (nil)
 -> 11)
;;  succ:       5
;;              4 (FALLTHRU)
;; basic block 4, loop depth 0, maybe hot
;;  prev block 3, next block 5, flags: (NEW, REACHABLE, RTL, MODIFIED)
;;  pred:       3 (FALLTHRU)
(note 94 9 10 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 10 94 11 4 (set (reg:DI 105)
        (reg:DI 0 ax)) "test1.cc":7:12 82 {*movdi_internal}
     (nil))
;;  succ:       5 (FALLTHRU)