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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110109] RISC-V: ICE when build the Intrinsic code Date: Sun, 04 Jun 2023 03:58:22 +0000 [thread overview] Message-ID: <bug-110109-4-FAQu6SnQwH@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-110109-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110109 --- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> --- (define_insn_and_split "*vlmul_extx2<mode>" [(set (match_operand:<VLMULX2> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX2> (match_operand:VLMULEXT2 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) (define_insn_and_split "*vlmul_extx4<mode>" [(set (match_operand:<VLMULX4> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX4> (match_operand:VLMULEXT4 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) (define_insn_and_split "*vlmul_extx8<mode>" [(set (match_operand:<VLMULX8> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX8> (match_operand:VLMULEXT8 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) (define_insn_and_split "*vlmul_extx16<mode>" [(set (match_operand:<VLMULX16> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX16> (match_operand:VLMULEXT16 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) (define_insn_and_split "*vlmul_extx32<mode>" [(set (match_operand:<VLMULX32> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX32> (match_operand:VLMULEXT32 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) (define_insn_and_split "*vlmul_extx64<mode>" [(set (match_operand:<VLMULX64> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX64> (match_operand:VLMULEXT64 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) I realize when I removed these patterns, issue is fixed. I am not sure whether it is correct fix since these patterns are existing in GCC13 which doesn't have such issue. The reason I add this patterns since GCC can not well handle subreg, If I simpily use emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); in "expand" stage, it can not assign regno(operands[0]) == regno (operands[1]) in RA, so I use constraint to force it. These patterns are performance optimization patterns. Should I remove those patterns and just use emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); in "expand" stage to fix this issue even though it demage the performance.
next prev parent reply other threads:[~2023-06-04 3:58 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-04 1:47 [Bug c/110109] New: " pan2.li at intel dot com 2023-06-04 1:56 ` [Bug target/110109] " pan2.li at intel dot com 2023-06-04 3:58 ` juzhe.zhong at rivai dot ai [this message] 2023-06-04 14:03 ` cvs-commit at gcc dot gnu.org 2023-06-04 15:48 ` law at gcc dot gnu.org
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