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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110109] RISC-V: ICE when build the Intrinsic code Date: Sun, 04 Jun 2023 14:03:29 +0000 [thread overview] Message-ID: <bug-110109-4-NaEsN6Lk3p@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-110109-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110109 --- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <panli@gcc.gnu.org>: https://gcc.gnu.org/g:a96ba6b958a00ad59c43cae10be65b263b5d0d2d commit r14-1531-ga96ba6b958a00ad59c43cae10be65b263b5d0d2d Author: Juzhe-Zhong <juzhe.zhong@rivai.ai> Date: Sun Jun 4 16:51:47 2023 +0800 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 This patch is to fix PR110109 issue. This issue happens is because: (define_insn_and_split "*vlmul_extx2<mode>" [(set (match_operand:<VLMULX2> 0 "register_operand" "=vr, ?&vr") (subreg:<VLMULX2> (match_operand:VLMULEXT2 1 "register_operand" " 0, vr") 0))] "TARGET_VECTOR" "#" "&& reload_completed" [(const_int 0)] { emit_insn (gen_rtx_SET (gen_lowpart (<MODE>mode, operands[0]), operands[1])); DONE; }) Such pattern generate such codes in insn-recog.cc: static int pattern57 (rtx x1) { rtx * const operands ATTRIBUTE_UNUSED = &recog_data.operand[0]; rtx x2; int res ATTRIBUTE_UNUSED; if (maybe_ne (SUBREG_BYTE (x1).to_constant (), 0)) return -1; ... PR110109 ICE at maybe_ne (SUBREG_BYTE (x1).to_constant (), 0) since for scalable RVV modes can not be accessed as SUBREG_BYTE (x1).to_constant () I create that patterns is to optimize the following test: vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) { return __riscv_vlmul_ext_v_f32mf2_f32m2(op1); } codegen: test_vlmul_ext_v_f32mf2_f32m2: vsetvli a5,zero,e32,m2,ta,ma vmv.v.i v2,0 vsetvli a5,zero,e32,mf2,ta,ma vle32.v v2,0(a1) vs2r.v v2,0(a0) ret There is a redundant 'vmv.v.i' here, Since GCC doesn't undefine IR (unlike LLVM, LLVM has undef/poison). For vlmul_ext_* RVV intrinsic, GCC will initiate all zeros into register. However, I think it's not a big issue after we support subreg livness tracking. PR target/110109 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Change expand approach. * config/riscv/vector.md (@vlmul_extx2<mode>): Remove it. (@vlmul_extx4<mode>): Ditto. (@vlmul_extx8<mode>): Ditto. (@vlmul_extx16<mode>): Ditto. (@vlmul_extx32<mode>): Ditto. (@vlmul_extx64<mode>): Ditto. (*vlmul_extx2<mode>): Ditto. (*vlmul_extx4<mode>): Ditto. (*vlmul_extx8<mode>): Ditto. (*vlmul_extx16<mode>): Ditto. (*vlmul_extx32<mode>): Ditto. (*vlmul_extx64<mode>): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr110109-1.c: New test. * gcc.target/riscv/rvv/base/pr110109-2.c: New test.
next prev parent reply other threads:[~2023-06-04 14:03 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-04 1:47 [Bug c/110109] New: " pan2.li at intel dot com 2023-06-04 1:56 ` [Bug target/110109] " pan2.li at intel dot com 2023-06-04 3:58 ` juzhe.zhong at rivai dot ai 2023-06-04 14:03 ` cvs-commit at gcc dot gnu.org [this message] 2023-06-04 15:48 ` law at gcc dot gnu.org
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