From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 8704E3858D28; Mon, 12 Jun 2023 00:15:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8704E3858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686528943; bh=vAJG9kjqWFYrpCBN8G3weIG4SghQ/S2zMUvdbJqXEME=; h=From:To:Subject:Date:In-Reply-To:References:From; b=shiZgP1umqnPtc3Jm4Cgva8h274ljPwNrqtQCWQ/j26AMbwevTo57Tcmyyn2PXDn/ qDA3YIH3/GnJFzk09ruV90GxAg/VmHqe90tpa95R8HcbE7XbWsHFukFMTv6BxtA/rb Ob7ftMwGh7mrirO/rzhhXwSRw4U5mqtohiA9pfh4= From: "jzhgonha at 163 dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110188] gcc for RISC-V stack aligned error Date: Mon, 12 Jun 2023 00:15:42 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.2.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: jzhgonha at 163 dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110188 --- Comment #6 from jzhgonha at 163 dot com --- thank you very much! =E5=8F=91=E8=87=AA=E6=88=91=E7=9A=84=E5=B0=8F=E7=B1=B3=E5=9C=A8 "kito at= gcc dot gnu.org" =EF=BC=8C2023=E5=B9=B46=E6=9C= =889=E6=97=A5 =E4=B8=8B=E5=8D=889:51=E5=86=99=E9=81=93=EF=BC=9A https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110188 Kito Cheng changed: What |Removed |Added =20=20=20=20 ---------------------------------------------------------------------------- CC| |kito at gcc dot gnu.org[1] --- Comment #5 from Kito Cheng --- Each stack area will align to 16 byte, that could be optimized in theory, but will complicate the frame layout implementation. ----sp - 0 a9 / outgoing stack arguments area ----sp - 4 / outgoing stack arguments area ----sp - 8 / outgoing stack arguments area ----sp - 12 / outgoing stack arguments area ----sp - 16 / GPR save area ----sp - 20 / GPR save area ----sp - 24 / GPR save area ----sp - 28 ra / GPR save area ----sp - 32 Complete layout has document in riscv.cc[2]: +-------------------------------+ | | | incoming stack arguments | | | +-------------------------------+ <-- incoming stack pointer | | | callee-allocated save area | | for arguments that are | | split between registers and | | the stack | | | +-------------------------------+ <-- arg_pointer_rtx | | | callee-allocated save area | | for register varargs | | | +-------------------------------+ <-- hard_frame_pointer_rtx; | | stack_pointer_rtx + gp_sp_offset | GPR save area | + UNITS_PER_WORD | | +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset | | + UNITS_PER_HWVALUE | FPR save area | | | +-------------------------------+ <-- frame_pointer_rtx (virtual) | | | local variables | | | P +-------------------------------+ | | | outgoing stack arguments | | | +-------------------------------+ <-- stack_pointer_rtx -- You are receiving this mail because: You reported the bug. 1. http://gnu.org 2. http://riscv.cc=