[Bug rtl-optimization/110206] [14 Regression] wrong code with -Os -march=cascadelake since r14-1246

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110206

--- Comment #19 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:eeb8e9a36d7aa9bc4ac8b0d7abe1e84e9afc4250

commit r12-9774-geeb8e9a36d7aa9bc4ac8b0d7abe1e84e9afc4250
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri Jul 14 11:46:22 2023 +0200

    cprop: Do not set REG_EQUAL note when simplifying paradoxical subreg
[PR110206]

    cprop1 pass does not consider paradoxical subreg and for (insn 22) claims
    that it equals 8 elements of HImodeby setting REG_EQUAL note:

    (insn 21 19 22 4 (set (reg:V4QI 98)
            (mem/u/c:V4QI (symbol_ref/u:DI ("*.LC1") [flags 0x2]) [0  S4 A32]))
"pr110206.c":12:42 1530 {*movv4qi_internal}
         (expr_list:REG_EQUAL (const_vector:V4QI [
                    (const_int -52 [0xffffffffffffffcc]) repeated x4
                ])
            (nil)))
    (insn 22 21 23 4 (set (reg:V8HI 100)
            (zero_extend:V8HI (vec_select:V8QI (subreg:V16QI (reg:V4QI 98) 0)
                    (parallel [
                            (const_int 0 [0])
                            (const_int 1 [0x1])
                            (const_int 2 [0x2])
                            (const_int 3 [0x3])
                            (const_int 4 [0x4])
                            (const_int 5 [0x5])
                            (const_int 6 [0x6])
                            (const_int 7 [0x7])
                        ])))) "pr110206.c":12:42 7471
{sse4_1_zero_extendv8qiv8hi2}
         (expr_list:REG_EQUAL (const_vector:V8HI [
                    (const_int 204 [0xcc]) repeated x8
                ])
            (expr_list:REG_DEAD (reg:V4QI 98)
                (nil))))

    We rely on the "undefined" vals to have a specific value (from the earlier
    REG_EQUAL note) but actual code generation doesn't ensure this (it doesn't
    need to).  That said, the issue isn't the constant folding per-se but that
    we do not actually constant fold but register an equality that doesn't
hold.

            PR target/110206

    gcc/ChangeLog:

            * fwprop.cc (contains_paradoxical_subreg_p): Move to ...
            * rtlanal.cc (contains_paradoxical_subreg_p): ... here.
            * rtlanal.h (contains_paradoxical_subreg_p): Add prototype.
            * cprop.cc (try_replace_reg): Do not set REG_EQUAL note
            when the original source contains a paradoxical subreg.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr110206.c: New test.

    (cherry picked from commit 1815e313a8fb519a77c94a908eb6dafc4ce51ffe)