From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 063EB3858414; Thu, 15 Jun 2023 07:59:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 063EB3858414 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686815945; bh=JAZAeaYMQ+cwKDUSgsRIm7P0QpRGQdNv0w+L2BfnUYw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=lKuImUMeaJw+6P1Ra3s5A3//4LD1KGloSwCugJiTrJ26Zl+vkgP+i+whx8KfGSijv Cu1pnVp2y7YjzHpRZ9Tf5L0ierccQWrZ9DbqZbYOi7bk2RikFDG1UIea+BEreyFYVQ gKyPYt5RhTNsfCFOSq+6HeI7pnBDUAq/Dj/HjQ9I= From: "juzhe.zhong at rivai dot ai" To: gcc-bugs@gcc.gnu.org Subject: [Bug c/110265] RISC-V: ICE when build RVV intrinsic with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13. Date: Thu, 15 Jun 2023 07:59:04 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: c X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: juzhe.zhong at rivai dot ai X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110265 --- Comment #1 from JuzheZhong --- This issue is caused by incorrect redcution instructions: (define_insn "@pred_reduc_" [(set (match_operand: 0 "register_operand" "=3Dvr, v= r") (unspec: [(unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI (vec_duplicate:VI (vec_select: (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) (match_operand:VI 3 "register_operand" " vr, vr"= )) (match_operand: 2 "vector_merge_operand" " vu, 0"= )] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) (define_insn "@pred_reduc_" [(set (match_operand: 0 "register_operand" "=3Dv= r,=20=20 vr") (unspec: [(unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI_ZVE64 (vec_duplicate:VI_ZVE64 (vec_select: (match_operand: 4 "register_operand" " vr,= =20=20 vr") (parallel [(const_int 0)]))) (match_operand:VI_ZVE64 3 "register_operand" " vr,= =20=20 vr")) (match_operand: 2 "vector_merge_operand" " vu,= =20=20=20 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) (define_insn "@pred_reduc_" [(set (match_operand: 0 "register_operand" "=3Dvd,= vd, vr, vr") (unspec: [(unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, r= K, rK, rK") (match_operand 6 "const_int_operand" " i, = i,=20 i, i") (match_operand 7 "const_int_operand" " i, = i,=20 i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI_ZVE32 (vec_duplicate:VI_ZVE32 (vec_select: (match_operand: 4 "register_operand" " vr, v= r, vr, vr") (parallel [(const_int 0)]))) (match_operand:VI_ZVE32 3 "register_operand" " vr, v= r, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, = 0, vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) This 3 patterns are using same iterators, but different attributes. For example, for VNx1QI reduction. The first pattern is pred_reduc_sumvnx1qivnx16qi (since vnx16qi is the LMUL= =3D 1mode for TARGET_MIN_VLEN >=3D 128). The first pattern is pred_reduc_sumvnx1qivnx8qi (since vnx8qi is the LMUL = =3D 1mode for TARGET_MIN_VLEN =3D=3D 64). The first pattern is pred_reduc_sumvnx1qivnx4qi (since vnx4qi is the LMUL = =3D 1mode for TARGET_MIN_VLEN =3D=3D 32). Even though their patterns name are different, but share same iterators same code_for They are all using code_for_reduc (UNSPEC, vnx1qi). We can't differentiate them. So the idea should be merge them into same pattern: (define_mode_iterator VQI [ =C2=A0 (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >=3D 128") ]) (define_mode_iterator VQI_LMUL1 [ =C2=A0 (VNx16QI "TARGET_MIN_VLEN >=3D 128") (VNx8QI "TARGET_MIN_VLEN =3D=3D= 64") (VNx4QI "TARGET_MIN_VLEN =3D=3D 32") ]) (define_insn "@pred_reduc_" =C2=A0 [(set (match_operand:VQI_LMUL1 0 "register_operand" =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0"=3Dvr, =C2=A0 vr") =C2=A0 (unspec:VQI_LMUL1 =C2=A0 =C2=A0 [(unspec: =C2=A0 =C2=A0 =C2=A0 =C2=A0[(match_operand: 1 "vector_mask_operand" =C2= =A0 =C2=A0 "vmWc1,vmWc1") =C2=A0 =C2=A0 =C2=A0 =C2=A0 (match_operand 5 "vector_length_operand" =C2=A0= =C2=A0 =C2=A0 =C2=A0" =C2=A0 rK, =C2=A0 rK") =C2=A0 =C2=A0 =C2=A0 =C2=A0 (match_operand 6 "const_int_operand" =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" =C2=A0 =C2=A0i, =C2=A0 =C2=A0i") =C2=A0 =C2=A0 =C2=A0 =C2=A0 (match_operand 7 "const_int_operand" =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" =C2=A0 =C2=A0i, =C2=A0 =C2=A0i") =C2=A0 =C2=A0 =C2=A0 =C2=A0 (reg:SI VL_REGNUM) =C2=A0 =C2=A0 =C2=A0 =C2=A0 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) =C2=A0 =C2=A0 =C2=A0(any_reduc:VQI =C2=A0 =C2=A0 =C2=A0 =C2=A0(vec_duplicate:VQI =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(vec_select: =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(match_operand:VQI_LMUL1 4 "regist= er_operand" " =C2=A0 vr, =C2=A0 vr") =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(parallel [(const_int 0)]))) =C2=A0 =C2=A0 =C2=A0 =C2=A0(match_operand:VQI 3 "register_operand" =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 " =C2=A0 vr, =C2=A0 vr")) =C2=A0 =C2=A0 =C2=A0(match_operand:VQI_LMUL1 2 "vector_merge_operand" =C2= =A0 " =C2=A0 vu, =C2=A0 =C2=A00")] UNSPEC_REDUC))] =C2=A0 "TARGET_VECTOR" =C2=A0 "vred.vs\t%0,%3,%4%p1" =C2=A0 [(set_attr "type" "vired") =C2=A0 =C2=A0(set_attr "mode" "")])=