From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 810063858D3C; Fri, 16 Jun 2023 23:37:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 810063858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686958663; bh=jVS9dB3WLLakVL8V6jvb1iVA4QtH9gQpmD1zgU+wYwg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=cAn21gYl+BmCQSr5giXgedRoMGWTkhdgCnOD3SMUPGIEPgjKZtIw4IC9fDXqP+GBv tOnQTG+fIdZwQ8gk+gLrbM9JM6Eh8K8xaYc6xYZ0cnbC58kLWoJQTn4/2hYXqO+RBI NTwQDNaFrUEyDMLirZvdiKUzZhz7Bs3Gr3kwUMwM= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug c/110265] RISC-V: ICE when build RVV intrinsic integer reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13. Date: Fri, 16 Jun 2023 23:37:42 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: c X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110265 --- Comment #2 from CVS Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:d0cf0c6c8449009697ad29dd7cb60e7f655628f2 commit r14-1899-gd0cf0c6c8449009697ad29dd7cb60e7f655628f2 Author: Pan Li Date: Fri Jun 16 15:01:46 2023 +0800 RISC-V: Bugfix for RVV integer reduction in ZVE32/64. The rvv integer reduction has 3 different patterns for zve128+, zve64 and zve32. They take the same iterator with different attributions. However, we need the generated function code_for_reduc (code, mode1, mode2). The implementation of code_for_reduc may look like below. code_for_reduc (code, mode1, mode2) { if (code =3D=3D max && mode1 =3D=3D VNx1QI && mode2 =3D=3D VNx1QI) return CODE_FOR_pred_reduc_maxvnx1qivnx16qi; // ZVE128+ if (code =3D=3D max && mode1 =3D=3D VNx1QI && mode2 =3D=3D VNx1QI) return CODE_FOR_pred_reduc_maxvnx1qivnx8qi; // ZVE64 if (code =3D=3D max && mode1 =3D=3D VNx1QI && mode2 =3D=3D VNx1QI) return CODE_FOR_pred_reduc_maxvnx1qivnx4qi; // ZVE32 } Thus there will be a problem here. For example zve32, we will have code_for_reduc (max, VNx1QI, VNx1QI) which will return the code of the ZVE128+ instead of the ZVE32 logically. This patch will merge the 3 patterns into pattern, and pass both the input_vector and the ret_vector of code_for_reduc. For example, ZVE32 w= ill be code_for_reduc (max, VNx1Q1, VNx8QI), then the correct code of ZVE32 will be returned as expectation. Please note both GCC 13 and 14 are impacted by this issue. Signed-off-by: Pan Li Co-Authored by: Juzhe-Zhong PR target/110265 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Add ret_mode for integer reduction expand. * config/riscv/vector-iterators.md: Add VQI, VHI, VSI and VDI, and the LMUL1 attr respectively. * config/riscv/vector.md (@pred_reduc_): Removed. (@pred_reduc_): Likewise. (@pred_reduc_): Likewise. (@pred_reduc_): New pattern. (@pred_reduc_): Likewise. (@pred_reduc_): Likewise. (@pred_reduc_): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr110265-1.c: New test. * gcc.target/riscv/rvv/base/pr110265-1.h: New test. * gcc.target/riscv/rvv/base/pr110265-2.c: New test. * gcc.target/riscv/rvv/base/pr110265-2.h: New test. * gcc.target/riscv/rvv/base/pr110265-3.c: New test.=