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* [Bug c/110299] New: RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.
@ 2023-06-18 9:20 pan2.li at intel dot com
2023-06-19 14:29 ` [Bug target/110299] " cvs-commit at gcc dot gnu.org
2023-09-07 10:33 ` kito at gcc dot gnu.org
0 siblings, 2 replies; 3+ messages in thread
From: pan2.li at intel dot com @ 2023-06-18 9:20 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299
Bug ID: 110299
Summary: RISC-V: ICE when build RVV intrinsic widen with
"-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and
13.
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: pan2.li at intel dot com
Target Milestone: ---
Created attachment 55358
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55358&action=edit
Reproduce code
Given we have the below code.
#include "riscv_vector.h"
#include "riscv_vector.h"
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t
scalar, size_t vl) {
return __riscv_vfwredosum_vs_f16m1_f32m1(vector, scalar, vl);
}
There will be the ICE when build similar as "riscv64-unknown-elf-gcc
-march=rv64gc_zve64d -mabi=lp64 -O3 -Wno-psabi -c -S test-float.c -o -".
.text
test-widen.c: In function 'test_vfwredosum_vs_f16m1_f32m1':
test-widen.c:4:10: error: invalid argument to built-in function
4 | return __riscv_vfwredosum_vs_f16m1_f32m1(vector, scalar, vl);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
during RTL pass: expand
test-widen.c:4:10: internal compiler error: Segmentation fault
0x1044343 crash_signal
../.././gcc/gcc/toplev.cc:314
0x7f76d0c4251f ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0xc5d1d7 store_expr(tree_node*, rtx_def*, int, bool, bool)
../.././gcc/gcc/expr.cc:6345
0xc5f500 expand_assignment(tree_node*, tree_node*, bool)
../.././gcc/gcc/expr.cc:6048
0xb2142c expand_call_stmt
../.././gcc/gcc/cfgexpand.cc:2829
0xb2142c expand_gimple_stmt_1
../.././gcc/gcc/cfgexpand.cc:3880
0xb2142c expand_gimple_stmt
../.././gcc/gcc/cfgexpand.cc:4044
0xb26770 expand_gimple_basic_block
../.././gcc/gcc/cfgexpand.cc:6096
0xb28837 execute
../.././gcc/gcc/cfgexpand.cc:6831
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/110299] RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.
2023-06-18 9:20 [Bug c/110299] New: RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13 pan2.li at intel dot com
@ 2023-06-19 14:29 ` cvs-commit at gcc dot gnu.org
2023-09-07 10:33 ` kito at gcc dot gnu.org
1 sibling, 0 replies; 3+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-06-19 14:29 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:
https://gcc.gnu.org/g:26bb67fc4d4b4bbefe298e21c965d41bb412eeb6
commit r14-1946-g26bb67fc4d4b4bbefe298e21c965d41bb412eeb6
Author: Pan Li <pan2.li@intel.com>
Date: Sun Jun 18 23:07:53 2023 +0800
RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
The rvv widdening reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1,
mode2).
The implementation of code_for_reduc may look like below.
code_for_reduc (code, mode1, mode2)
{
if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+
if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf; // ZVE64
if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf; // ZVE32
}
Thus there will be a problem here. For example zve32, we will have
code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
the ZVE128+ instead of the ZVE32 logically.
This patch will merge the 3 patterns into pattern, and pass both the
input_vector and the ret_vector of code_for_reduc. For example, ZVE32
will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of
ZVE32
will be returned as expectation.
Please note both GCC 13 and 14 are impacted by this issue.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
PR target/110299
* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
modes.
* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
VF_ZVE63 and VF_ZVE32.
* config/riscv/vector.md
(@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New
pattern.
(@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.
gcc/testsuite/ChangeLog:
PR target/110299
* gcc.target/riscv/rvv/base/pr110299-1.c: New test.
* gcc.target/riscv/rvv/base/pr110299-1.h: New test.
* gcc.target/riscv/rvv/base/pr110299-2.c: New test.
* gcc.target/riscv/rvv/base/pr110299-2.h: New test.
* gcc.target/riscv/rvv/base/pr110299-3.c: New test.
* gcc.target/riscv/rvv/base/pr110299-3.h: New test.
* gcc.target/riscv/rvv/base/pr110299-4.c: New test.
* gcc.target/riscv/rvv/base/pr110299-4.h: New test.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/110299] RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.
2023-06-18 9:20 [Bug c/110299] New: RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13 pan2.li at intel dot com
2023-06-19 14:29 ` [Bug target/110299] " cvs-commit at gcc dot gnu.org
@ 2023-09-07 10:33 ` kito at gcc dot gnu.org
1 sibling, 0 replies; 3+ messages in thread
From: kito at gcc dot gnu.org @ 2023-09-07 10:33 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299
Kito Cheng <kito at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
CC| |kito at gcc dot gnu.org
Resolution|--- |FIXED
--- Comment #2 from Kito Cheng <kito at gcc dot gnu.org> ---
Fixed on trunk
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-06-18 9:20 [Bug c/110299] New: RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13 pan2.li at intel dot com
2023-06-19 14:29 ` [Bug target/110299] " cvs-commit at gcc dot gnu.org
2023-09-07 10:33 ` kito at gcc dot gnu.org
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