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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110406] d: Wrong code-gen returning POD structs by value
Date: Mon, 26 Jun 2023 04:28:28 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110406

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ABI

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #5)
> (In reply to ibuclaw from comment #3)
> > (In reply to Andrew Pinski from comment #2)
> > > >structs have been set the wrong mode
> > >=20
> > > No, they don't have wrong mode, just the x86_64 backend is broken, se=
e bug
> > > 102027 comment #7 specifically.
> > I think they do.
> >=20
> > On 64-bit,  I expect the mode set by compute_record_mode to be TImode.=
=20
> > However what I'm instead seeing is BLKmode. This tells me I might be ca=
lling
> > it too early, and some fields yet to have their DECL_SIZE set.
>=20
> Unless the struct has the alignment of TImode, it should be BLKmode ...

here is a C testcase to get it returned into vector register (incorrectly d=
ue
to the alignment being set to 32):
```
typedef unsigned uint;
struct  cpuid_abcd_t
{
    uint eax;
    uint ebx;
    uint ecx;
    uint edx;
}  __attribute__((aligned(8*4)));

struct cpuid_abcd_t
cpuid_insn(const uint in_eax)
{
        struct cpuid_abcd_t ret=3D{};

        asm (
            "cpuid"
            :
                "=3Da" ( ret.eax ),
                "=3Db" ( ret.ebx ),
                "=3Dc" ( ret.ecx ),
                "=3Dd" ( ret.edx )
            :
                "a"  ( in_eax )
            :
    );
        return ret;
}
```

Which itself is GCC 12+ regression too ...=