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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110411] ICE on simple memcpy test case when allowing
 generation of vector pair load/store insns
Date: Tue, 14 Nov 2023 13:37:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110411

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by jeevitha <jeevitha@gcc.gnu.o=
rg>:

https://gcc.gnu.org/g:4b1f59c1c1ca9bc24fbf7dbfce81a99153b3a933

commit r13-8064-g4b1f59c1c1ca9bc24fbf7dbfce81a99153b3a933
Author: Jeevitha <jeevitha@linux.ibm.com>
Date:   Thu Aug 31 05:40:18 2023 -0500

    rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

    There are no instructions that do traditional AltiVec addresses (i.e.
    with the low four bits of the address masked off) for OOmode and XOmode
    objects. The solution is to modify the constraints used in the movoo and
    movxo pattern to disallow these types of addresses, which assists LRA in
    resolving this issue. Furthermore, the mode size 16 check has been
    removed in vsx_quad_dform_memory_operand to allow OOmode and XOmode, and
    quad_address_p already handles less than size 16.

    2023-08-31  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>

    gcc/
            PR target/110411
            * config/rs6000/mma.md (define_insn_and_split movoo): Disallow
            AltiVec address operands.
            (define_insn_and_split movxo): Likewise.
            * config/rs6000/predicates.md (vsx_quad_dform_memory_operand):
Remove
            redundant mode size check.

    gcc/testsuite/
            PR target/110411
            * gcc.target/powerpc/pr110411-1.c: New testcase.
            * gcc.target/powerpc/pr110411-2.c: New testcase.

    (cherry picked from commit 9ea1248604d7b65009af32103814332f35bd33e2)=