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From: "luke.geeson at cs dot ucl.ac.uk" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/110573] branch delay slots are not filled with
 atomic stores
Date: Thu, 06 Jul 2023 23:44:36 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110573

--- Comment #4 from Luke Geeson <luke.geeson at cs dot ucl.ac.uk> ---
Ah so since atomics are treated as volatile (like LLVM) instructions that
access them cannot inhabit a delay slot. Is it still valid to treat atomics=
 as
volatile?

Consider the following MIPS litmus test:
```
{ %x0=3Dx; %y0=3Dy; %y1=3Dy; %x1=3Dx; }
 P0           | P1           ;
 lw $2,0(%x0) | lw $2,0(%y1) ;
 ori $3,$0,1  | ori $3,$0,1  ;
 sw $3,0(%y0) | sw $3,0(%x1) ;

exists (0:$2=3D1 /\ 1:$2=3D1)
```
When run under the mips model we do not observe the outcome in the exists
clause:
```
0:$2=3D0; 1:$2=3D0;
0:$2=3D0; 1:$2=3D1;
0:$2=3D1; 1:$2=3D0;
```
That is, from an ordering perspective it is unlikely that unexpected behavi=
ours
can occur - in this case putting sw in a delay slot should be ok (the same
doesn't hold for RISC-V/Arm models of course).

I understand treating atomics as volatile has historical precedent but a ca=
se
can be made, at least on modern architectures and with improved understandi=
ng
of models, that atomics are not volatile and more optimisations can be appl=
ied.
What do you think?=