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From: "koachan+gccbugs at protonmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110592] New: [SPARC] GCC should default to TSO memory model when compiling for sparc32 Date: Sat, 08 Jul 2023 01:46:55 +0000 [thread overview] Message-ID: <bug-110592-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110592 Bug ID: 110592 Summary: [SPARC] GCC should default to TSO memory model when compiling for sparc32 Product: gcc Version: 12.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: koachan+gccbugs at protonmail dot com Target Milestone: --- Created attachment 55501 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55501&action=edit Reproducer of unwanted memory reordering under TSO processors Currently, when targeting sparc32 processors, GCC assumes that the hardware has sequentially consistent memory ordering by default. This can cause problems when running generated binaries on v8 and later processors, which uses weaker TSO ordering. In the attached reproducer, when compiled with the default sparc32 target, the resulting code is missing the required barriers: 00000fb0 <thread1Func()>: ... 104c: e0 26 00 00 st %l0, [ %i0 ] 1050: c2 06 40 00 ld [ %i1 ], %g1 1054: c2 26 80 00 st %g1, [ %i2 ] ... 0000108c <thread2Func()>: ... 1128: e0 26 00 00 st %l0, [ %i0 ] 112c: c2 06 40 00 ld [ %i1 ], %g1 1130: c2 26 80 00 st %g1, [ %i2 ] ... Compare with the result when explicitly specifying -mcpu=v8: 00000fa4 <thread1Func()>: ... 1040: e0 26 00 00 st %l0, [ %i0 ] 1044: c0 6b bf ff ldstub [ %sp + -1 ], %g0 1048: c0 6b bf ff ldstub [ %sp + -1 ], %g0 104c: c2 06 40 00 ld [ %i1 ], %g1 1050: c2 26 80 00 st %g1, [ %i2 ] 1054: c0 6b bf ff ldstub [ %sp + -1 ], %g0 ... 0000108c <thread2Func()>: ... 1128: e0 26 00 00 st %l0, [ %i0 ] 112c: c0 6b bf ff ldstub [ %sp + -1 ], %g0 1130: c0 6b bf ff ldstub [ %sp + -1 ], %g0 1134: c2 06 40 00 ld [ %i1 ], %g1 1138: c2 26 80 00 st %g1, [ %i2 ] 113c: c0 6b bf ff ldstub [ %sp + -1 ], %g0 ... This causes the default-target code to hit the assert condition. Since all code that works on TSO processors will work on processors with a stronger memory model (i.e sequential consistency), it is probably better if GCC uses TSO by default unless otherwise specified (e.g by explicitly using -mcpu=v7).
next reply other threads:[~2023-07-08 1:46 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-08 1:46 koachan+gccbugs at protonmail dot com [this message] 2023-07-08 8:25 ` [Bug target/110592] " ebotcazou at gcc dot gnu.org 2023-07-08 9:42 ` ebotcazou at gcc dot gnu.org 2023-07-09 13:02 ` martin at netbsd dot org 2023-07-09 17:47 ` ebotcazou at gcc dot gnu.org 2023-07-10 13:19 ` campbell+gcc-bugzilla at mumble dot net 2023-07-12 9:31 ` ebotcazou at gcc dot gnu.org 2023-07-12 12:17 ` campbell+gcc-bugzilla at mumble dot net 2023-07-12 14:58 ` koachan+gccbugs at protonmail dot com 2023-07-12 17:16 ` ebotcazou at gcc dot gnu.org 2023-07-12 20:36 ` campbell+gcc-bugzilla at mumble dot net
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