From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 61B7B38582BE; Wed, 12 Jul 2023 13:13:14 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 61B7B38582BE
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1689167594;
	bh=NjUGbeVTHR+v69bsIekpwmokc+XKXIOGNyIiKWeLJuA=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=qvuUydCVn+Jeav9jMctx+Yx7himC0p3tOQdgoquYSv+wLi50Mq404As6WvWyok8YR
	 wLDkO0xAL9ocughdcK2DICSGrNxyGHktzkOqt0n+2WmwUrIgr2jZNy8+/RElTSnWul
	 1ClOKvuhaOG2g7ft7cyHd7vMK1XrprVlb9lAavus=
From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110598] [14 Regression] wrong code on llvm-14.0.6 due to
 memcmp being miscompiled
Date: Wed, 12 Jul 2023 13:13:13 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: wrong-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: cvs-commit at gcc dot gnu.org
X-Bugzilla-Status: ASSIGNED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: roger at nextmovesoftware dot com
X-Bugzilla-Target-Milestone: 14.0
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-110598-4-O5Gfd55xSs@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-110598-4@http.gcc.gnu.org/bugzilla/>
References: <bug-110598-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110598

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:d2c18b4a16f9e1a6ed271ec1efaf94533d1c4a94

commit r14-2465-gd2c18b4a16f9e1a6ed271ec1efaf94533d1c4a94
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Wed Jul 12 14:12:34 2023 +0100

    PR target/110598: Fix rega =3D 0; rega ^=3D rega regression in i386.md

    This patch fixes the regression PR target/110598 caused by my recent
    addition of a peephole2.  The intention of that optimization was to
    simplify zeroing a register, followed by an IOR, XOR or PLUS operation
    on it into a move, or as described in the comment:
    ;; Peephole2 rega =3D 0; rega op=3D regb into rega =3D regb.

    The issue is that I'd failed to consider the (rare and unusual) case,
    where regb is rega, where the transformation leads to the incorrect
    "rega =3D rega", when it should be "rega =3D 0".  The minimal fix is to
    add a !reg_mentioned_p check to the recent peephole2.

    In addition to resolving the regression, I've added a second peephole2
    to optimize the problematic case above, which contains a false
    dependency and is therefore tricky to optimize elsewhere.  This is an
    improvement over GCC 13, for example, that generates the redundant:

            xorl    %edx, %edx
            xorq    %rdx, %rdx

    2023-07-12  Roger Sayle  <roger@nextmovesoftware.com>

    gcc/ChangeLog
            PR target/110598
            * config/i386/i386.md (peephole2): Check !reg_mentioned_p when
            optimizing rega =3D 0; rega op=3D regb for op in [XOR,IOR,PLUS].
            (peephole2): Simplify rega =3D 0; rega op=3D rega cases.

    gcc/testsuite/ChangeLog
            PR target/110598
            * gcc.target/i386/pr110598.c: New test case.=