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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/110701] [14 Regression] Wrong code at
 -O1/2/3/s on x86_64-linux-gnu
Date: Mon, 17 Jul 2023 17:51:08 +0000
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X-Bugzilla-Component: rtl-optimization
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X-Bugzilla-Keywords: wrong-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110701

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |wrong-code
   Last reconfirmed|                            |2023-07-17
   Target Milestone|---                         |14.0
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

Trying 16 -> 17:
   16: {r94:HI=3Dr92:DI#0^0x3;clobber flags:CC;}
      REG_DEAD r92:DI
      REG_UNUSED flags:CC
   17: r95:SI=3Dsign_extend(r94:HI)
      REG_DEAD r94:HI
Successfully matched this instruction:
(set (reg:SI 95)
    (ior:SI (subreg:SI (reg:DI 92) 0)
        (const_int 3 [0x3])))
allowing combination of insns 16 and 17
original costs 4 + 4 =3D 8
replacement cost 4
deferring deletion of insn with uid =3D 16.
modifying insn i3    17: {r95:SI=3Dr92:DI#0|0x3;clobber flags:CC;}
      REG_UNUSED flags:CC
      REG_DEAD r92:DI
deferring rescan insn with uid =3D 17.


BUT r92 is defined by
(insn 12 11 13 2 (parallel [
            (set (reg:DI 92)
                (ashiftrt:DI (reg:DI 93 [ bD.2759 ])
                    (const_int 63 [0x3f])))
            (clobber (reg:CC 17 flags))
        ]) "/app/example.cpp":6:53 901 {ashrdi3_cvt}
     (expr_list:REG_DEAD (reg:DI 93 [ bD.2759 ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (expr_list:REG_EQUAL (ashiftrt:DI (mem/c:DI (symbol_ref:DI ("b")
[flags 0x2]  <var_decl 0x7f6efc025d80 b>) [1 bD.2759+0 S8 A64])
                    (const_int 63 [0x3f]))
                (nil)))))
(insn 13 12 14 2 (set (subreg:HI (reg:DI 92) 0)
        (not:HI (subreg:HI (reg:DI 92) 0))) "/app/example.cpp":6:53 816
{*one_cmplhi2_1}
     (nil))
(insn 14 13 16 2 (parallel [
            (set (subreg:HI (reg:DI 92) 0)
                (and:HI (subreg:HI (reg:DI 92) 0)
                    (const_int 340 [0x154])))
            (clobber (reg:CC 17 flags))
        ]) "/app/example.cpp":6:53 596 {*andhi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))

So that should be ok, well no because SI !=3D HI here ... and=