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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/110717] Double-word sign-extension
 missed-optimization
Date: Thu, 20 Jul 2023 19:19:56 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110717

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |krebbel at gcc dot gnu.org,
                   |                            |law at gcc dot gnu.org,
                   |                            |rsandifo at gcc dot gnu.or=
g,
                   |                            |segher at gcc dot gnu.org

--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Wonder how many important targets provide double-word shift patterns vs. on=
es
which expand it through generic code.
aarch64 looks quite small:
foo:
        extr    x1, x1, x0, 5
        asr     x1, x1, 59
        ret
powerpc probably could be improved:
foo:
        srwi 9,4,5
        mr 10,9
        rlwimi 4,9,5,0,31-5
        rlwimi 10,3,27,0,31-27
        srawi 3,10,27
        blr
ditto s390x:
foo:
        lg      %r1,0(%r3)
        lg      %r3,8(%r3)
        srlg    %r5,%r3,5
        lghi    %r0,31
        sllg    %r1,%r1,59
        ogr     %r1,%r5
        ngr     %r3,%r0
        sllg    %r5,%r5,5
        srag    %r1,%r1,59
        ogr     %r3,%r5
        stg     %r3,8(%r2)
        stg     %r1,0(%r2)
        br      %r14
ditto riscv64:
foo:
        srli    a5,a0,5
        slli    a1,a1,59
        or      a1,a5,a1
        slli    a5,a1,5
        andi    a0,a0,31
        or      a0,a5,a0
        srai    a1,a1,59
        ret=