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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/110717] Double-word sign-extension
 missed-optimization
Date: Thu, 20 Jul 2023 18:56:34 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110717

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:b50a851eef4b70aabf28fa875d9b2a302d17b66a

commit r14-2684-gb50a851eef4b70aabf28fa875d9b2a302d17b66a
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu Jul 20 20:54:51 2023 +0200

    i386: Double-word sign-extension missed-optimization [PR110717]

    When sign-extending the value in a double-word register pair using shift
and
    ashiftrt sequence with the same count immediate value less than word wi=
dth,
    there is no need to shift the lower word of the value. The sign-extensi=
on
    could be limited to the upper word, but we uselessly shift the lower wo=
rd
    with it as well:
            movq    %rdi, %rax
            movq    %rsi, %rdx
            shldq   $59, %rdi, %rdx
            salq    $59, %rax
            shrdq   $59, %rdx, %rax
            sarq    $59, %rdx
            ret
    for -m64 and
            movl    4(%esp), %eax
            movl    8(%esp), %edx
            shldl   $27, %eax, %edx
            sall    $27, %eax
            shrdl   $27, %edx, %eax
            sarl    $27, %edx
            ret
    for -m32.

    The patch introduces a new post-reload splitter to provide the combined
    ASHIFTRT/SHIFT instruction pattern.  The instruction is split to a sequ=
ence
    of SAL and SAR insns with the same count immediate operand:
            movq    %rsi, %rdx
            movq    %rdi, %rax
            salq    $59, %rdx
            sarq    $59, %rdx
            ret

    Some complication is required to properly handle STV transform, where we
    emit a sequence with DImode PSLLQ and PSRAQ insns for 32-bit AVX512VL
    targets when profitable.

    The patch also fixes a small oversight and enables STV transform of SIm=
ode
    ASHIFTRT to PSRAD also for SSE2 targets.

            PR target/110717

    gcc/ChangeLog:

            * config/i386/i386-features.cc
            (general_scalar_chain::compute_convert_gain): Calculate gain
            for extend higpart case.
            (general_scalar_chain::convert_op): Handle
            ASHIFTRT/ASHIFT combined RTX.
            (general_scalar_to_vector_candidate_p): Enable ASHIFTRT for
            SImode for SSE2 targets.  Handle ASHIFTRT/ASHIFT combined RTX.
            * config/i386/i386.md (*extend<dwi>2_doubleword_highpart):
            New define_insn_and_split pattern.
            (*extendv2di2_highpart_stv): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr110717.c: New test.=