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From: "palmer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110748] RISC-V: optimize store of DF 0.0
Date: Thu, 20 Jul 2023 17:22:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110748

--- Comment #7 from palmer at gcc dot gnu.org ---
(In reply to palmer from comment #6)
> (In reply to Jeffrey A. Law from comment #5)
> > I'd bet it's const_0_operand not allowing CONST_DOUBLE.
> >=20
> > The question is what unintended side effects we'd have if we allowed
> > CONST_DOUBLE 0.0 in const_0_operand.
>=20
> We don't have a architectural 0 register, so we'd probably end up needing=
 to
> refactor some stuff.  It's probably smoother to add some sort of
> "reg_or_0_or_0f_operand" type predicate, and then convert the floating-po=
int
> stuff that takes X registers over to that (at least stores and
> integer->float conversions, but maybe some comparisons too?).

Should have said "We don't have a architectural 0 floating-point register",=
 we
have x0 (which is why that reg_or_0 stuff shows up).=