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From: "vineetg at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110748] RISC-V: optimize store of DF 0.0
Date: Tue, 15 Aug 2023 17:13:32 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110748

--- Comment #16 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #15)

> On the branch devel/vineetg/optim-double-const-m0 I have double -0.0 work=
ing.
>=20
> znd:
>         li      a5,-1
>         slli    a5,a5,63
>         sd      a5,0(a0)
>         ret
>=20
> There's currently an ICE for zbs
>=20
> IRA is undoing the split so the insn with const_int 0x80000000_00000000
> doesn't exist for final pass.
>=20
> expand
> ------
> (insn 6 3 0 2 (set (mem:DF (reg:DI 135)
>         (const_double:DF -0.0 [-0x0.0p+0])) {*movdf_hardfloat_rv64}
>=20
> split1
> -----
> (insn 10 3 11 2 (set (reg:DI 136)
>         (const_int [0x8000000000000000]))
>=20
> (insn 11 10 0 2 (set (mem:DF (reg:DI 135)
>         (subreg:DF (reg:DI 136) 0))
>=20
> ira
> ----
> (insn 11 9 12 2 (set (mem:DF (reg:DI 135)
>         (const_double:DF -0.0 [-0x0.0p+0])) {*movdf_hardfloat_rv64}

So IRA is doing the equivalent replacement for a register which is referenc=
ed
exactly twice: set once and used once, w/o any reg pressure considerations =
[1].

[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627212.html

There seems to be no easy way around it.=