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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110751] RISC-V: Suport undefined value that allows
 VSETVL PASS use TA/MA
Date: Wed, 13 Sep 2023 09:48:32 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110751

--- Comment #36 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Richard Biener from comment #34)
> The ELSE value of type TYPE would be constructed like
>=20
>  tree var =3D create_tmp_var (type);
>  tree else_val =3D get_or_create_ssa_default_def (cfun, var);
>=20
> I'm not sure const0_rtx is a good representation on RTL - how would
> you distinguish that from a conditional operation on an integer vector
> with else value zero?  Say for an integer division?

My current approach is that I passed scalar 0 to the ELSE VALUE.

So in the I relax the operand predicate of the cond_len else operand:

it can be either a register_operand has VECTOR_MODE or a const_int 0 (Note =
that
it
can't be the CONST_VECTOR).

So, I can distinguish the else operand. If it is a scalar const_int 0, it is
undefine. Otherwise, it is always a register operand with a vector mode.=