From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 65DC5385696E; Thu, 20 Jul 2023 12:35:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 65DC5385696E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689856507; bh=JG+bX5wkGm8nCKTgI+yUjdoNZf6y42aDmbjJpB/7HYM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=VC/XWJkImZF02XWaFuHix8iLupku4D1b/TfTuSP3BwXQQtAKuBUKxDX0MuSN9Wwdp CcfzS6kU0oYzYJt1qCnAsDp/QXFunk3S5iicVDxk13JNO179for35u7Gq2TfydE+NL z+11BI7JcuaLjAL0JpYFYrUpuKW9JaMX+rOYi+7Q= From: "rguenther at suse dot de" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA Date: Thu, 20 Jul 2023 12:35:07 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenther at suse dot de X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110751 --- Comment #8 from rguenther at suse dot de --- On Thu, 20 Jul 2023, juzhe.zhong at rivai dot ai wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110751 >=20 > --- Comment #6 from JuzheZhong --- > (In reply to rguenther@suse.de from comment #5) > > On Thu, 20 Jul 2023, kito at gcc dot gnu.org wrote: > >=20 > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110751 > > >=20 > > > --- Comment #4 from Kito Cheng --- > > > > OK, so TA is either merge or all-ones. > > >=20 > > > Yes, your understand is correct, just few more detail is that can be = mixing > > > with either merge or all-ones. > > >=20 > > > e.g. > > >=20 > > > An 4 x i32 vector with mask 1 0 1 0 > > >=20 > > > Op =3D | a | b | c | d | > > > Mask =3D | 1 | 0 | 1 | 0 | > > >=20 > > > the result could be: > > > | a | b | c | d | > > > | a | all-1 | c | d | > > > | a | all-1 | c | all-1 | > > > | a | all-1 | c | d | > > >=20 > > >=20 > > > > Not sure how you can use MA at the moment since you specify an exis= ting operand in your target hook. As far as > > > > I can see there's no value the target hook can provide that matches= any > > > of the implementation semantics? > > >=20 > > > That's the key point - we don't know how to return an undefined value= there, we > > > have intrinsic can generate undefined value, but it seems impossible = to > > > generate that within the hook. > >=20 > > Well, neither *A nor *U can be specified currently. As said for 'merge' > > we would need another operand. And since 'unspecified' is either merge > > or all-ones we can't express that either. It's not really 'undefined' > > either. > >=20 > > Note this also means the proposal to define a .MASK_LOAD as zeroing > > masked elements is not going to work for RISC-V, instead we'd need > > an explicit 'else' value there as well. > >=20 > > In fact we could follow .MASK_LOAD for .COND_* and simply omit > > the 'else' operand for the case of 'unspecified', no? GIMPLE would > > be fine omitting it, not sure whether there's precedent for > > optabs with optional operands? >=20 > For RVV auto-vectorization, we define COND_LEN_* has else value in the > arguments. But the else value is not always the real value we need to > care about, this is the code from vectorizable_operation: >=20 > if (reduc_idx >=3D 0) > { > /* Perform the operation on active elements only and take > inactive elements from the reduction chain input. */ > gcc_assert (!vop2); > vops.quick_push (reduc_idx =3D=3D 1 ? vop1 : vop0); > } > else > { > auto else_value =3D targetm.preferred_else_value > (cond_fn, vectype, vops.length () - 1, &vops[1]); > vops.quick_push (else_value); > } >=20 >=20 > You can see for reduction operations, the else value is the real value we > need to depend on, we should use "TU" (Undisturbed or merge value) in RVV. > Meaning the inactive elements should remain the "old" value that's why we > use "TU". Sure. For the above case that's obviously correct. > However, for single binary operations for example, division, we just only > need to forbid the division operations of the inactive elements in the=20 > hardware, we don't care the value of the inactive elements value. so in > this case, we want to use "TA". In this case, we want the else value be > a meaningless placeholder in Gimple IR (similar to "undef" or "poison" in > LLVM). >=20 > Such meaningless placeholder in the argument of Gimple IR, can be benefic= ail > for RVV for 2 following reasons: > 1. allow us use "TA". > 2. Doesn't consume a register. >=20 > I am not sure whether we can represent such placeholder in Gimple IR. As said, just drop the 'else' operand and assign 'unspecified' to its semantics? Like we do for .LEN_MASK_LOAD where there isn't any 'else' value and I presume you'll use 'TA' as well there?=