From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 363743858412; Thu, 21 Sep 2023 09:13:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 363743858412 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1695287608; bh=OlBij3GSEv42mF7jNUj/K61jRjGsnTdWzgCh8t6Wimc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=DDot3z56qj18Zj91S4xVUEFc/iSbdyBrTlJlSoq3jeDpAEFoHVYwvJh7mMUd59ufj meela+Y74LwuWxuqPxudbCmWGOHhH0KPCJcGq/FIO9h/N7iK+8pjFoccWbRfUiLBVM zFgaCkJHyaAdnW4Pix5gERCvrnjclMXGMjbRB/Bc= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA Date: Thu, 21 Sep 2023 09:13:15 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110751 --- Comment #43 from CVS Commits --- The trunk branch has been updated by Lehua Ding : https://gcc.gnu.org/g:9b5b2c9f95056f97cf95f0e8d970015aa586497b commit r14-4194-g9b5b2c9f95056f97cf95f0e8d970015aa586497b Author: Juzhe-Zhong Date: Thu Sep 21 15:19:29 2023 +0800 RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] Now GCC middle-end can support undefined value which is traslated into (scratch:mode). This patch is to enable RISC-V backend undefine value in ELSE value of COND_LEN_xxx/COND_xxx. Consider this following case: __attribute__((noipa)) void vrem_int8_t (int8_t * __restrict dst, int8_t * __restrict a, int= 8_t * __restrict b, int n) { for (int i =3D 0; i < n; i++) dst[i] =3D a[i] % b[i]; } Before this patch: vrem_int8_t: ble a3,zero,.L5 vsetvli a5,zero,e8,m1,ta,ma vmv.v.i v4,0 ---> redundant. .L3: vsetvli a5,a3,e8,m1,tu,ma ---> should be TA. vmv1r.v v1,v4 ---> redudant. vle8.v v3,0(a1) vle8.v v2,0(a2) sub a3,a3,a5 vrem.vv v1,v3,v2 vse8.v v1,0(a0) add a1,a1,a5 add a2,a2,a5 add a0,a0,a5 bne a3,zero,.L3 .L5: ret After this patch: vrem_int8_t: ble a3,zero,.L5 .L3: vsetvli a5,a3,e8,m1,ta,ma vle8.v v1,0(a1) vle8.v v2,0(a2) sub a3,a3,a5 vrem.vv v1,v1,v2 vse8.v v1,0(a0) add a1,a1,a5 add a2,a2,a5 add a0,a0,a5 bne a3,zero,.L3 .L5: ret PR target/110751 gcc/ChangeLog: * config/riscv/autovec.md: Enable scratch rtx in ELSE operand. * config/riscv/predicates.md (autovec_else_operand): New predic= ate. * config/riscv/riscv-v.cc (get_else_operand): New function. (expand_cond_len_unop): Adapt ELSE value. (expand_cond_len_binop): Ditto. (expand_cond_len_ternop): Ditto. * config/riscv/riscv.cc (riscv_preferred_else_value): New funct= ion. (TARGET_PREFERRED_ELSE_VALUE): New targethook. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adapt test. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Ditto.=