[Bug target/110762] inappropriate use of SSE (or AVX) insns for v2sf mode operations

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110762

--- Comment #19 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:ade30fad6669e5f34ca4c587c724d74ecc953175

commit r14-2786-gade30fad6669e5f34ca4c587c724d74ecc953175
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Wed Jul 26 11:10:46 2023 +0200

    i386: Clear upper half of XMM register for V2SFmode operations [PR110762]

    Clear the upper half of a V4SFmode operand register in front of all
    potentially trapping instructions. The testcase:

    --cut here--
    typedef float v2sf __attribute__((vector_size(8)));
    typedef float v4sf __attribute__((vector_size(16)));

    v2sf test(v4sf x, v4sf y)
    {
      v2sf x2, y2;

      x2 = __builtin_shufflevector (x, x, 0, 1);
      y2 = __builtin_shufflevector (y, y, 0, 1);

      return x2 + y2;
    }
    --cut here--

    now compiles to:

            movq    %xmm1, %xmm1    # 9     [c=4 l=4]  *vec_concatv4sf_0
            movq    %xmm0, %xmm0    # 10    [c=4 l=4]  *vec_concatv4sf_0
            addps   %xmm1, %xmm0    # 11    [c=12 l=3]  *addv4sf3/0

    This approach addresses issues with exceptions, as well as issues with
    denormal/invalid values. An obvious exception to the rule is a division,
    where the value != 0.0 should be loaded into the upper half of the
    denominator to avoid division by zero exception.

    The patch effectively tightens the solution from PR95046 by clearing upper
    halves of all operand registers before every potentially trapping
instruction.
    The testcase:

    --cut here--
    typedef float __attribute__((vector_size(8))) v2sf;

    v2sf test (v2sf a, v2sf b, v2sf c)
    {
      return a * b - c;
    }
    --cut here--

    compiles to:

            movq    %xmm1, %xmm1    # 8     [c=4 l=4]  *vec_concatv4sf_0
            movq    %xmm0, %xmm0    # 9     [c=4 l=4]  *vec_concatv4sf_0
            movq    %xmm2, %xmm2    # 12    [c=4 l=4]  *vec_concatv4sf_0
            mulps   %xmm1, %xmm0    # 10    [c=16 l=3]  *mulv4sf3/0
            movq    %xmm0, %xmm0    # 13    [c=4 l=4]  *vec_concatv4sf_0
            subps   %xmm2, %xmm0    # 14    [c=12 l=3]  *subv4sf3/0

    The implementation emits V4SFmode operation, so we can remove all
"emulated"
    SSE2 V2SFmode trapping instructions and remove "emulated" SSE2 V2SFmode
    alternatives from 3dNOW! insn patterns.

            PR target/110762

    gcc/ChangeLog:

            * config/i386/i386.md (plusminusmult): New code iterator.
            * config/i386/mmx.md (mmxdoublevecmode): New mode attribute.
            (movq_<mode>_to_sse): New expander.
            (<plusminusmult:insn>v2sf3): Macroize expander from addv2sf3,
            subv2sf3 and mulv2sf3 using plusminusmult code iterator.  Rewrite
            as a wrapper around V4SFmode operation.
            (mmx_addv2sf3): Change operand 1 and operand 2 predicates to
            nonimmediate_operand.
            (*mmx_addv2sf3): Remove SSE alternatives.  Change operand 1 and
            operand 2 predicates to nonimmediate_operand.
            (mmx_subv2sf3): Change operand 2 predicate to nonimmediate_operand.
            (mmx_subrv2sf3): Change operand 1 predicate to
nonimmediate_operand.
            (*mmx_subv2sf3): Remove SSE alternatives.  Change operand 1 and
            operand 2 predicates to nonimmediate_operand.
            (mmx_mulv2sf3): Change operand 1 and operand 2 predicates to
            nonimmediate_operand.
            (*mmx_mulv2sf3): Remove SSE alternatives.  Change operand 1 and
            operand 2 predicates to nonimmediate_operand.
            (divv2sf3): Rewrite as a wrapper around V4SFmode operation.
            (<smaxmin:code>v2sf3): Ditto.
            (mmx_<smaxmin:code>v2sf3): Change operand 1 and operand 2
            predicates to nonimmediate_operand.
            (*mmx_<smaxmin:code>v2sf3): Remove SSE alternatives.  Change
            operand 1 and operand 2 predicates to nonimmediate_operand.
            (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
            (sqrtv2sf2): Rewrite as a wrapper around V4SFmode operation.
            (*mmx_haddv2sf3_low): Ditto.
            (*mmx_hsubv2sf3_low): Ditto.
            (vec_addsubv2sf3): Ditto.
            (*mmx_maskcmpv2sf3_comm): Remove.
            (*mmx_maskcmpv2sf3): Remove.
            (vec_cmpv2sfv2si): Rewrite as a wrapper around V4SFmode operation.
            (vcond<V2FI:mode>v2sf): Ditto.
            (fmav2sf4): Ditto.
            (fmsv2sf4): Ditto.
            (fnmav2sf4): Ditto.
            (fnmsv2sf4): Ditto.
            (fix_truncv2sfv2si2): Ditto.
            (fixuns_truncv2sfv2si2): Ditto.
            (mmx_fix_truncv2sfv2si2): Remove SSE alternatives.
            Change operand 1 predicate to nonimmediate_operand.
            (floatv2siv2sf2): Rewrite as a wrapper around V4SFmode operation.
            (floatunsv2siv2sf2): Ditto.
            (mmx_floatv2siv2sf2): Remove SSE alternatives.
            Change operand 1 predicate to nonimmediate_operand.
            (nearbyintv2sf2): Rewrite as a wrapper around V4SFmode operation.
            (rintv2sf2): Ditto.
            (lrintv2sfv2si2): Ditto.
            (ceilv2sf2): Ditto.
            (lceilv2sfv2si2): Ditto.
            (floorv2sf2): Ditto.
            (lfloorv2sfv2si2): Ditto.
            (btruncv2sf2): Ditto.
            (roundv2sf2): Ditto.
            (lroundv2sfv2si2): Ditto.
            (*mmx_roundv2sf2): Remove.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr110762.c: New test.