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From: "sainan+gcc.bugzilla at calamity dot gg" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/110773] [Aarch64] crash (SIGBUS) due to atomic
 instructions on under-aligned memory
Date: Thu, 04 Apr 2024 17:09:09 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110773

--- Comment #5 from Sainan <sainan+gcc.bugzilla at calamity dot gg> ---
(In reply to Wilco from comment #4)
> The atomic will also set correct struct alignment.

My thinking was that maybe this is not the case (=3D standard library issue)
since both GCC and Clang seem to be causing this issue, but manually adding
alignas(16) also didn't help.

> You would get a crash if you build for LSE so you get a LDADDAL instructi=
on
> and then run it on a CPU that doesn't. So try -mcpu=3Dnative and it should
> work.

-mcpu=3Dnative didn't fix the SIGBUS, only removed __aarch64_ldadd4_acq_rel=
 from
the stack trace.

FWIW, the CPU on this system where I get the SIGBUS is Cortex-A76, which sh=
ould
support LSE and atomics, but it seems everytime it encounters atomics, it j=
ust
throws a SIGBUS. It works fine on Snapdragon 8cx Gen 3.=