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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110788] Spilling to mask register for GPR vec_duplicate
Date: Thu, 27 Jul 2023 11:29:42 +0000 [thread overview]
Message-ID: <bug-110788-4-wCNP3YkQG8@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110788-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110788
--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #0)
> I suppose it could also be a missed optimization in REE since I think
> the HImode regs should already be zero-extended?
No, only SImode moves have implicit zero extensions. Plain HImode and QImode
moves behave as inserts into the lowpart of the wide register.
next prev parent reply other threads:[~2023-07-27 11:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 8:40 [Bug target/110788] New: " rguenth at gcc dot gnu.org
2023-07-27 7:02 ` [Bug target/110788] " crazylht at gmail dot com
2023-07-27 7:09 ` crazylht at gmail dot com
2023-07-27 11:29 ` ubizjak at gmail dot com [this message]
2023-07-27 13:55 ` crazylht at gmail dot com
2023-07-28 2:07 ` cvs-commit at gcc dot gnu.org
2023-07-28 2:30 ` crazylht at gmail dot com
2023-11-30 10:51 ` liuhongt at gcc dot gnu.org
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