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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110790] [14 Regression] gcc -m32 generates invalid bit
 test code on gmp-6.2.1
Date: Sun, 12 Nov 2023 20:15:46 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110790

--- Comment #9 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to Andrew Pinski from comment #8)
> I need some code generation help for gcc.target/i386/pr110790-2.c, I have=
 a
> patch where we now generate:
> ```
>         movq    (%rdi,%rax,8), %rax
>         shrq    %cl, %rax
>         andl    $1, %eax
> ```
>=20
> instead of previously:
> ```
>         movq    (%rdi,%rax,8), %rax
>         btq     %rsi, %rax
>         setc    %al
>         movzbl  %al, %eax
> ```
>=20
> I suspect the sequence that contains shrq/and is better but I am 100% sur=
e.
> We still get btq when used with a conditional too.

The new sequence is better. It does not create a partial reg write (setc ne=
eds
a clearing XOR in fron of CC-setting instruction).=