From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id B5DB63858D32; Fri,  4 Aug 2023 09:16:15 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B5DB63858D32
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1691140575;
	bh=P8X8X5cf1/jd1I4IgE53o9O0SLFVGmgOR9/lNvn6nMU=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=ehn6jzefWwKQwHResz+U2Snx9pcQxP1+wQgMuhUNwpY2CvkVH54Q2w5bQ9xkDkwb9
	 CDYpsFx9VwmlQK5hfE0+UXib/ylHzP9OI6OwzLKwxo/yiFTjMnAt1fzfYhF3UDYrj4
	 IdTiRNtfLYg+dlO06iikKElfUUbXIPeKJT/2ppns=
From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/110897] RISC-V: Fail to vectorize shift
Date: Fri, 04 Aug 2023 09:16:14 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: tree-optimization
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: missed-optimization
X-Bugzilla-Severity: normal
X-Bugzilla-Who: rguenth at gcc dot gnu.org
X-Bugzilla-Status: NEW
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-110897-4-WANwn93zFJ@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-110897-4@http.gcc.gnu.org/bugzilla/>
References: <bug-110897-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D110897

--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #5)
> (In reply to Richard Biener from comment #3)
> > it looks like you don't support vector short logical shift?  For some r=
eason
> > vect_recog_over_widening_pattern doesn't check whether the demoted oper=
ation
> > is supported ...
> >=20
> > The following helps on x86_64, it disables the demotion.  I think the i=
dea
> > was that we eventually recognize a widening shift, so the narrow operat=
ion
> > itself doesn't need to be supported, but clearly that doesn't work out
> > when there is no such shift.
> >=20
> > diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc
> > index e4ab8c2d65b..4e4191652e3 100644
> > --- a/gcc/tree-vect-patterns.cc
> > +++ b/gcc/tree-vect-patterns.cc
> > @@ -3091,6 +3091,11 @@ vect_recog_over_widening_pattern (vec_info *vinf=
o,
> >    if (!new_vectype || !op_vectype)
> >      return NULL;
> >=20=20
> > +  optab optab;
> > +  if (!(optab =3D optab_for_tree_code (code, op_vectype, optab_vector))
> > +      || optab_handler (optab, TYPE_MODE (op_vectype)) =3D=3D CODE_FOR=
_nothing)
> > +    return NULL;
> > +
> >    if (dump_enabled_p ())
> >      dump_printf_loc (MSG_NOTE, vect_location, "demoting %T to %T\n",
> >                      type, new_type);
> >=20
> > with the patch above x86 can vectorize both loops with AVX2 but not wit=
hout.
> >=20
> > Can you confirm this helps on RISC-V as well?
> >=20
> > Richard, what was the idea here?
>=20
> Hi, Richi.
>=20
> I guess you mean "vector short logical shift" pattern is this:
>=20
> (define_insn_and_split "v<optab><mode>3"
>   [(set (match_operand:VI 0 "register_operand"  "=3Dvr,vr")
>     (any_shift:VI
>      (match_operand:VI 1 "register_operand"     " vr,vr")
>      (match_operand:VI 2 "vector_shift_operand" " vr,vk")))]
>   "TARGET_VECTOR && can_create_pseudo_p ()"
>   "#"
>   "&& 1"
>   [(const_int 0)]
> {
>   riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
> 				 riscv_vector::RVV_BINOP, operands);
>   DONE;
> }
>  [(set_attr "type" "vshift")
>   (set_attr "mode" "<MODE>")])
>=20
> (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
>=20
> VI includes vector short.
>=20
> I think RISCV port support vector short logical shift ?

The optab is vlshr_optab:

OPTAB_VC(vlshr_optab, "vlshr$a3", LSHIFTRT)=20

your define_insn maybe produces the wrong names?=