From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A23A33858401; Fri, 18 Aug 2023 12:03:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A23A33858401 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692360191; bh=pcm0Dekp8X7XdfcntqVK0y/1LxihdbBoH/jDCdKKDPI=; h=From:To:Subject:Date:In-Reply-To:References:From; b=uVJ+OziZ25y16bWtYBFfukOQUKt50USYqrHlDXAx0QxBaMOQoOz1Q0PIZt1sjnWf4 ocx4CPsfmcotyUusvjJJKdWA/bdzf1vBWUguO0vtDwelba+z5XakUWE0TnTw0jBWnW FbVH9DoXWJnJgNeaLBL+pxi9/rJdHXBWaBl8L4No= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/111010] [13/14 regression] error: unable to find a register to spill compiling GCDAProfiling.c since r13-5092-g4e0b504f26f78f Date: Fri, 18 Aug 2023 12:03:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.2.1 X-Bugzilla-Keywords: ice-on-valid-code, missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc keywords Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111010 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |uros at gcc dot gnu.org, | |vmakarov at gcc dot gnu.org Keywords| |ice-on-valid-code, | |missed-optimization, ra --- Comment #6 from Richard Biener --- The culprit hardly is responsible - it's the RA failing, this can be fixed = for example by using -fschedule-insns -fsched-pressure. I think this define-insn-and-split is a bit heavy-weight for i386 and a spl= it after reload given we allow arbitrary memory operands (in this case the addressing modes are simple though) (insn 109 283 243 9 (set (reg:DI 295) (ior:DI (ashift:DI (zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI 329 [orig:229 _118 ] [229]) (const_int 4 [0x4])) (reg/f:SI 328 [orig:83 a.0_1 ] [83])) [3 MEM[(unsigned int *)_11]+0 S4 A32])) (const_int 32 [0x20])) (zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI 294 [233]) (const_int 4 [0x4])) (reg/f:SI 328 [orig:83 a.0_1 ] [83])) [3 MEM[(unsig= ned int *)_15]+0 S4 A32])))) "t.c":15:7 680 {*concatsidi3_3} (expr_list:REG_DEAD (reg/f:SI 328 [orig:83 a.0_1 ] [83]) (expr_list:REG_DEAD (reg:SI 329 [orig:229 _118 ] [229]) (expr_list:REG_DEAD (reg:SI 294 [233]) (nil))))) this requires 5 GPRs (and it's not even the most complicated form of addressing). I'm not sure if LRA is supposed to fix this up, spilling the two MEMs will still result in 5 registers needed, and with 32bits that's somewhat difficult to have? So IMHO this is a bug in the machine description. The LRA dump isn't really enlightening, it seems to succeed for the above insn: 0 Non input pseudo reload: reject++ 1 Non pseudo reload: reject++ Cycle danger: overall +=3D LRA_MAX_REJECT alt=3D0,overall=3D608,losers=3D1,rld_nregs=3D1 0 Non pseudo reload: reject++ 1 Non pseudo reload: reject++ alt=3D1,overall=3D2,losers=3D0,rld_nregs=3D0 Choosing alt 1 in insn 239: (0) m (1) re {*movsi_internal} Creating newreg=3D292 from oldreg=3D97, assigning class GENERAL_REGS = to address r292 Creating newreg=3D293 from oldreg=3D157, assigning class INDEX_REGS to address r293 Change to class INDEX_REGS for r292 Creating newreg=3D294 from oldreg=3D233, assigning class INDEX_REGS to address r294 1 Non-pseudo reload: reject+=3D2 1 Non input pseudo reload: reject++ 3 Non-pseudo reload: reject+=3D2 3 Non input pseudo reload: reject++ alt=3D0,overall=3D18,losers=3D2,rld_nregs=3D2 0 Non-pseudo reload: reject+=3D2 0 Non input pseudo reload: reject++ 3 Non-pseudo reload: reject+=3D2 3 Non input pseudo reload: reject++ alt=3D1,overall=3D18,losers=3D2,rld_nregs=3D3 0 Non-pseudo reload: reject+=3D2 0 Non input pseudo reload: reject++ 1 Non-pseudo reload: reject+=3D2 1 Non input pseudo reload: reject++ alt=3D2,overall=3D18,losers=3D2,rld_nregs=3D3 0 Non-pseudo reload: reject+=3D2 0 Non input pseudo reload: reject++ 0 Early clobber: reject++ alt=3D3,overall=3D10,losers=3D1,rld_nregs=3D2 Choosing alt 3 in insn 109: (0) &r (1) m (3) m {*concatsidi3_3} Creating newreg=3D295, assigning class GENERAL_REGS to r295 109: r295:DI=3Dzero_extend([r229:SI*0x4+r83:SI])<<0x20|zero_extend([r294:SI*0x4+= r83:SI]) REG_DEAD r233:SI REG_DEAD r229:SI Inserting insn reload before: 240: r292:SI=3Dr97:SI 241: r293:SI=3Dr157:SI 242: r294:SI=3Dr233:SI Inserting insn reload after: 243: [r292:SI+r293:SI+0x8]=3Dr295:DI but then the ICE is very much later ... ****** Splitting a hard reg after assignment #2: ****** Hard reg 0 is preferable by r350 with profit 174 EMERGENCY DUMP:=