[Bug target/111112] New: RISC-V: Resulting more vsetvl instructions of vwadd + vadd but not vwadd + vwadd

[Bug target/111112] New: RISC-V: Resulting more vsetvl instructions of vwadd + vadd but not vwadd + vwadd

[lehua.ding at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111112

            Bug ID: 111112
           Summary: RISC-V: Resulting more vsetvl instructions of vwadd +
                    vadd  but not vwadd + vwadd
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lehua.ding at rivai dot ai
  Target Milestone: ---

For GCC, first res = b[i] + c[i], than res += promoted_d
For Clang, first res = promoted_d + b[i], than res += c[i]
Resulting more vsetvl instructions when using GCC's method
since vwadd and vadd need different type.

https://godbolt.org/z/9vexWjccn

C Code:
void __attribute__ ((noipa))
f (SIGNEDNESS char *restrict a, SIGNEDNESS char *restrict b,
   SIGNEDNESS char *restrict c, SIGNEDNESS char d)
{
  int promoted_d = d;
  for (int i = 0; i < 8; ++i)
    /* Deliberate use of signed >>.  */
    a[i] = ( promoted_d + b[i] + c[i]) >> 2;
}

RISC-V GCC:
f:
        vsetivli        zero,8,e16,m1,ta,ma
        vle8.v  v4,0(a1)
        vle8.v  v3,0(a2)
        vmv.v.x v2,a3
        vsetvli zero,zero,e8,mf2,ta,ma
        vwadd.vv        v1,v4,v3
        vsetvli zero,zero,e16,m1,ta,ma
        vadd.vv v1,v1,v2
        vsetvli zero,zero,e8,mf2,ta,ma
        vnsra.wi        v1,v1,2
        vse8.v  v1,0(a0)
        ret

RISC-V Clang:
f:                                      # @f
        vsetivli        zero, 8, e8, mf2, ta, ma
        vle8.v  v8, (a1)
        vle8.v  v9, (a2)
        vwadd.vx        v10, v8, a3
        vwadd.wv        v10, v10, v9
        vnsrl.wi        v8, v10, 2
        vse8.v  v8, (a0)
        ret