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From: "seurer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug testsuite/111216] New: [14 regression] instructions counts for
 vector tests change after r14-3258-ge7a36e4715c716
Date: Mon, 28 Aug 2023 18:32:08 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111216

            Bug ID: 111216
           Summary: [14 regression] instructions counts for vector tests
                    change after r14-3258-ge7a36e4715c716
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: testsuite
          Assignee: unassigned at gcc dot gnu.org
          Reporter: seurer at gcc dot gnu.org
  Target Milestone: ---

g:e7a36e4715c7162ccfd7cd32da985d629bbd9c61, r14-3258-ge7a36e4715c716

FAIL: gcc.target/powerpc/fold-vec-logical-ors-char.c scan-assembler-times
\\mxxlnor\\M 1
FAIL: gcc.target/powerpc/fold-vec-logical-ors-char.c scan-assembler-times
\\mxxlor\\M 7
FAIL: gcc.target/powerpc/fold-vec-logical-ors-int.c scan-assembler-times
\\mxxlnor\\M 1
FAIL: gcc.target/powerpc/fold-vec-logical-ors-int.c scan-assembler-times
\\mxxlor\\M 7
FAIL: gcc.target/powerpc/fold-vec-logical-ors-longlong.c scan-assembler-tim=
es
\\mxxlnor\\M 3
FAIL: gcc.target/powerpc/fold-vec-logical-ors-longlong.c scan-assembler-tim=
es
\\mxxlor\\M 9
FAIL: gcc.target/powerpc/fold-vec-logical-ors-short.c scan-assembler-times
\\mxxlnor\\M 1
FAIL: gcc.target/powerpc/fold-vec-logical-ors-short.c scan-assembler-times
\\mxxlor\\M 7
FAIL: gcc.target/powerpc/fold-vec-logical-other-char.c scan-assembler-times
\\mxxlnand\\M 3
FAIL: gcc.target/powerpc/fold-vec-logical-other-int.c scan-assembler-times
\\mxxlnand\\M 3
FAIL: gcc.target/powerpc/fold-vec-logical-other-longlong.c scan-assembler-t=
imes
\\mxxlnand\\M 3
FAIL: gcc.target/powerpc/fold-vec-logical-other-short.c scan-assembler-times
\\mxxlnand\\M 3

These are all just instruction count tests so the changes may not matter.

commit e7a36e4715c7162ccfd7cd32da985d629bbd9c61 (HEAD)
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Wed Aug 16 22:28:50 2023 -0600

    [PATCH] RISC-V: Support simplify (-1-x) for vector.=