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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111232] RISC-V: Failed to combine vwmul + vadd into
 vwmacc
Date: Wed, 06 Sep 2023 09:56:39 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111232

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Lehua Ding <lhtin@gcc.gnu.org>:

https://gcc.gnu.org/g:9ee40b9a7bee83394fc7ba6fef71cb76d91b49c8

commit r14-3735-g9ee40b9a7bee83394fc7ba6fef71cb76d91b49c8
Author: Lehua Ding <lehua.ding@rivai.ai>
Date:   Mon Sep 4 17:15:08 2023 +0800

    RISC-V: Keep vlmax vector operators in simple form until split1 pass

    This patch keep vlmax vector pattern in simple before split1 pass which
    will allow more optimization (e.g. combine) before split1 pass.
    This patch changes the vlmax pattern in autovec.md to define_insn_and_s=
plit
    as much as possible and clean up some combine patterns that are no long=
er
needed.
    This patch also fixed PR111232 bug which was caused by a combined faile=
d.

            PR target/111232

    gcc/ChangeLog:

            * config/riscv/autovec-opt.md
(@pred_single_widen_mul<any_extend:su><mode>):
            Delete.
            (*pred_widen_mulsu<mode>): Delete.
            (*pred_single_widen_mul<mode>): Delete.
            (*dual_widen_<any_widen_binop:optab><any_extend:su><mode>):
            Add new combine patterns.
            (*single_widen_sub<any_extend:su><mode>): Ditto.
            (*single_widen_add<any_extend:su><mode>): Ditto.
            (*single_widen_mult<any_extend:su><mode>): Ditto.
            (*dual_widen_mulsu<mode>): Ditto.
            (*dual_widen_mulus<mode>): Ditto.
            (*dual_widen_<optab><mode>): Ditto.
            (*single_widen_add<mode>): Ditto.
            (*single_widen_sub<mode>): Ditto.
            (*single_widen_mult<mode>): Ditto.
            * config/riscv/autovec.md (<optab><mode>3):
            Change define_expand to define_insn_and_split.
            (<optab><mode>2): Ditto.
            (abs<mode>2): Ditto.
            (smul<mode>3_highpart): Ditto.
            (umul<mode>3_highpart): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testca=
ses.
            * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditt=
o.
            * gcc.target/riscv/rvv/autovec/pr111232.c: New test.=