From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 38D693858C5E; Mon, 2 Oct 2023 15:07:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38D693858C5E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1696259254; bh=E64xskOEGYbR8tdn7nUZM9Zxq5eJZfAEBZZ6KkruSoY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=nHqXmsclFs1buq2QRxnArjsxqZqEypr6ecJ8sg4QrJ8rL3RtDhSMvUWr2L2H1xut/ MjGcUztC5RO7+t81rG3+FwOPLaLiRCjhovVVjgG2UmyWWP3wiEVWBGu55TLzOFxu0i y0BCicFAL68cb+CxBI9kcywcfbwA4//9nXwwtzcw= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/111235] [Armv7-a]: Control-dependency between atomic accesses removed by -O1. Date: Mon, 02 Oct 2023 15:07:33 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: wilco at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111235 --- Comment #2 from CVS Commits --- The master branch has been updated by Wilco Dijkstra : https://gcc.gnu.org/g:0731889c026bfe8d55c4851422ca5ec9d037f7a0 commit r14-4365-g0731889c026bfe8d55c4851422ca5ec9d037f7a0 Author: Wilco Dijkstra Date: Fri Sep 29 13:21:10 2023 +0100 Arm: Block predication on atomics [PR111235] The v7 memory ordering model allows reordering of conditional atomic instructions. To avoid this, make all atomic patterns unconditional. Expand atomic loads and stores for all architectures so the memory acce= ss can be wrapped into an UNSPEC. Reviewed-by: Ramana Radhakrishnan gcc/ChangeLog: PR target/111235 * config/arm/constraints.md: Remove Pf constraint. * config/arm/sync.md (arm_atomic_load): Add new pattern. (arm_atomic_load_acquire): Likewise. (arm_atomic_store): Likewise. (arm_atomic_store_release): Likewise. (atomic_load): Switch patterns to define_expand. (atomic_store): Likewise. (arm_atomic_loaddi2_ldrd): Remove predication. (arm_load_exclusive): Likewise. (arm_load_acquire_exclusive): Likewise. (arm_load_exclusivesi): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_load_exclusivedi): Likewise. (arm_load_acquire_exclusivedi): Likewise. (arm_store_exclusive): Likewise. (arm_store_release_exclusivedi): Likewise. (arm_store_release_exclusive): Likewise. * config/arm/unspecs.md: Add VUNSPEC_LDR and VUNSPEC_STR. gcc/testsuite/ChangeLog: PR target/111235 * gcc.dg/rtl/arm/stl-cond.c: Remove test. * gcc.target/arm/atomic_loaddi_7.c: Fix dmb count. * gcc.target/arm/atomic_loaddi_8.c: Likewise. * gcc.target/arm/pr111235.c: Add new test.=