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From: "mkuvyrkov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/111267] [14 Regression] Codegen regression
 from i386 argument passing changes
Date: Thu, 25 Jan 2024 09:48:43 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111267

--- Comment #15 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
(In reply to Maxim Kuvyrkov from comment #13)
> We are seeing scan-assembler failures in a single 32-bit arm test.  This
> affects both linux and bare-metal targets: arm-linux-gnueabihf and
> arm-none-eabi.
>=20
> 		=3D=3D=3D gcc tests =3D=3D=3D
>=20
> Running gcc:gcc.target/arm/arm.exp ...
> FAIL: gcc.target/arm/bics_3.c scan-assembler-times bics\tr[0-9]+, r[0-9]+,
> r[0-9]+ 2
> FAIL: gcc.target/arm/bics_3.c scan-assembler-times bics\tr[0-9]+, r[0-9]+,
> r[0-9]+, .sl #2 1

I've looked into the reason for the above failures, and it seems to be not =
an
issue.

After the patch fwprop1 decides to do an additional propagation, which was
considered as "would increase complexity of pattern" before the patch.  This
results in change from "bics; mov" to "bic; subs".  If I understand ARM
assembler correctly, handling of sign was shifted from "bics" to "subs"
instruction.

This is the actual code: BEFORE:
        bics    r0, r0, r1      @ 9     [c=3D4 l=3D4]=20
*andsi_notsi_si_compare0_scratch
        mov     r0, #1  @ 23    [c=3D4 l=3D4]  *thumb2_movsi_vfp/1
        it      eq
        moveq   r0, #0  @ 26    [c=3D8 l=3D4]  *p *thumb2_movsi_vfp/2
        bx      lr      @ 29    [c=3D8 l=3D4]  *thumb2_return

and AFTER:
        bic     r0, r0, r1      @ 8     [c=3D4 l=3D4]  andsi_notsi_si
        subs    r0, r0, #0      @ 22    [c=3D4 l=3D4]  cmpsi2_addneg/0
        it      ne
        movne   r0, #1  @ 23    [c=3D8 l=3D4]  *p *thumb2_movsi_vfp/2
        bx      lr      @ 26    [c=3D8 l=3D4]  *thumb2_return

If I don't hear anything to the contrary, I'll update the testcase to accept
both "bic" and "bics".=