From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id BBC0C3858C52; Sat, 9 Sep 2023 07:16:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BBC0C3858C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694243815; bh=UlMqfzzBHoKZx47LdAwSsKzHmZCbENVd7CY4jpvMJc8=; h=From:To:Subject:Date:In-Reply-To:References:From; b=C5nGnPs1VkR/iU/rLsNnpKycxvyM+exbzQz7alPBkAkIfNqUaVcnwkVOZEpjk6HbU AcJ1UakNiABaim3I7YIo8OMpNjaYzai0SgGQfGUcLah5P4GMDQ1cdQrMcF5aAz027B esdwngJEQjHN56Retf9nQa50av8dimuP3U8kwzrg= From: "chenglulu at loongson dot cn" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/111334] [14 regression] ICE is reported during the combine pass optimization Date: Sat, 09 Sep 2023 07:16:54 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: chenglulu at loongson dot cn X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111334 --- Comment #16 from chenglulu --- (In reply to Xi Ruoyao from comment #15) > (In reply to chenglulu from comment #13) > > (In reply to Xi Ruoyao from comment #12) > > > (In reply to chenglulu from comment #11) > > > > (In reply to Xi Ruoyao from comment #10) > > > > > (In reply to Xi Ruoyao from comment #9) > > > > >=20 > > > > > > (define_insn "di3_fake" > > > > > > [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") > > > > > > - (sign_extend:DI > > > > > > - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") > > > > > > - (match_operand:DI 2 "register_operand" "r,r,r"))))] > > > > > > - "" > > > > > > + (if_then_else > > > > > > + (and (eq (match_operand:DI 1 "register_operand" "r,r,0") > > > > > > + (sign_extend:DI (subreg:SI (match_dup 1) 0))) > > > > > > + (eq (match_operand:DI 2 "register_operand" "r,r,r") > > > > > > + (sign_extend:DI (subreg:SI (match_dup 2) 0)))) > > > > > > + (sign_extend:DI > > > > > > + (any_div:SI (subreg:SI (match_dup 1) 0) > > > > > > + (subreg:SI (match_dup 2) 0))) > > > > > > + (unspec:DI [(const_int 0)] UNSPEC_BAD_DIVW)))] > > > > >=20 > > > > > With this the compiler will still believe all bad {div,mod}.w{,u} > > > >=20 > > > > I think this is already defined as UNSPEC. Isn=E2=80=99t the simple= r the logic, the > > > > better? > > >=20 > > > Yes, I think we should just use 4 different UNSPEC_ values and the si= mple > > > version. But I've not find a way to use 4 different UNSPEC_ values i= n the > > > RTL template except duplicating everything 4 times... > >=20 > > I still have a question that I don't quite understand, that is, why tha= t the > > four generated strings are equivalent when using an UNSPEC name? My tem= plate > > names are different, and they will not be automatically matched during > > optimization.??? >=20 > Oh I get it, you mean >=20 > (define_insn "di3_fake" > [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") > (sign_extend:DI > - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") > - (match_operand:DI 2 "register_operand" "r,r,r"))))] > + (unspec:DI [(any_div:DI > + (match_operand:DI 1 "register_operand" "r,r,0") > + (match_operand:DI 2 "register_operand" "r,r,r"))] > + UNSPEC_ANY_DIV)))] > "" > { > return loongarch_output_division (".w\t%0,%1,%2", operands); >=20 > Good idea! I think it's better than my stupid hacks :). >=20 > I'd been thinking about: >=20 > (define_insn "di3_fake" > [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") > (sign_extend:DI > - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") > - (match_operand:DI 2 "register_operand" "r,r,r"))))] > + (unspec:DI [(match_operand:DI 1 "register_operand" "r,r,0") > + (match_operand:DI 2 "register_operand" "r,r,r")] > + UNSPEC_ANY_DIV)))] > "" > { > return loongarch_output_division (".w\t%0,%1,%2", operands); >=20 > and this is just wrong. Is it better to modify it this way? --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -60,6 +60,7 @@ (define_c_enum "unspec" [ ;; Stack tie UNSPEC_TIE + UNSPEC_ANY_DIV ;; CRC UNSPEC_CRC UNSPEC_CRCC @@ -900,7 +901,7 @@ (define_expand "3" (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) =3D=3D SImode) + if (GET_MODE (operands[0]) =3D=3D SImode && TARGET_64BIT) { rtx reg1 =3D gen_reg_rtx (DImode); rtx reg2 =3D gen_reg_rtx (DImode); @@ -938,9 +939,12 @@ (define_insn "*3" (define_insn "di3_fake" [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") (sign_extend:DI - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") - (match_operand:DI 2 "register_operand" "r,r,r"))))] - "" + (unspec:SI + [(subreg:SI + (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") + (match_operand:DI 2 "register_operand" "r,r,r")) 0= )] + UNSPEC_ANY_DIV)))] + "TARGET_64BIT" { return loongarch_output_division (".w\t%0,%1,%2", operands);=