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From: "chenglulu at loongson dot cn" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111334] [14 regression] ICE is reported during the
 combine pass optimization
Date: Fri, 08 Sep 2023 06:02:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111334

--- Comment #7 from chenglulu <chenglulu at loongson dot cn> ---
(In reply to Xi Ruoyao from comment #6)
> (In reply to Xi Ruoyao from comment #5)
> > (In reply to chenglulu from comment #3)
> > > This involves the template <optab>di3_fake:
> > > (define_insn "<optab>di3_fake"
> > >   [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r")
> > >         (sign_extend:DI
> > >           (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
> > >                       (match_operand:DI 2 "register_operand" "r,r,r")=
)))]
> > >   ""
> > > {
> > >   return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands=
);
> > > }
> > >   [(set_attr "type" "idiv")
> > >    (set_attr "mode" "SI")
> > >    (set (attr "enabled")
> > >       (if_then_else
> > >         (match_test "!!which_alternative =3D=3D loongarch_check_zero_=
div_p()")
> > >         (const_string "yes")
> > >         (const_string "no")))])
> > >=20
> > >=20
> > > I think there is a problem with the implementation of this template.=
=20
> > > First, the instructions generated in the template are [u]div.w[u], et=
c. The
> > > description of such instructions in the instruction manual is that if=
 the
> > > upper 32 bits are not extended by the 31st bit sign then the result is
> > > uncertain.
> >=20
> > I think this reason alone makes the pattern looks very wrong.
> >=20
> > I'll take a look...
>=20
> Hmm, I guess we should just make di3_fake an UNSPEC because there is no w=
ay
> to use div.w and its friends out of <optab:any_div><mode>3.

I agree with your idea, so I tried changing it to something like this.Do you
think it's okay for me to change like this?


(define_insn "<optab>di3_fake"
  [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r")
        (sign_extend:DI
          (unspec:SI [(any_div:SI (match_operand:DI 1 "register_operand"
"r,r,0")
                      (match_operand:DI 2 "register_operand" "r,r,r"))]
           UNSPEC_ANY_DIV)))]
  ""
{
  return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
  [(set_attr "type" "idiv")
   (set_attr "mode" "SI")
   (set (attr "enabled")
      (if_then_else
        (match_test "!!which_alternative =3D=3D loongarch_check_zero_div_p(=
)")
        (const_string "yes")
        (const_string "no")))])=