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From: "jeremy.bennett at embecosm dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during
 get_avl_or_vl_reg (vsetvl pass)
Date: Tue, 12 Sep 2023 08:04:47 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111375

--- Comment #2 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
(In reply to JuzheZhong from comment #1)
> I can't reproduce the ICE in your testcase with same command.
>=20
> ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/
> install/bin/riscv64-unknown-linux-gnu-gfortran -w -march=3Drv64gcv -mabi=
=3Dlp64d
> -c -Ofast -ftree-vectorize --param=3Driscv-autovec-preference=3Dscalable =
bug.f90
>=20
>=20
> No ICE.
>=20
> Could you help me with that ?

Hi  JuzheZhong

I built with the following components:

Repository           SHA-1 hash (commit ID)=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20
----------           ----------------------=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20
gcc                  316d57da5bb9205b946afc56d78582fee874e4b5
binutils-gdb         9a343d2bb57c4555dedad9b43907aeeda7b51dae
glibc                073edbdfabaad4786e974a451efe4b6b3f7a5a61

Is this the same as you? I'll do a clean rebuild with the latest tool chain=
 in
case this problem has been fixed.=