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* [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) @ 2023-09-11 18:21 jeremy.bennett at embecosm dot com 2023-09-12 8:01 ` [Bug middle-end/111375] " juzhe.zhong at rivai dot ai ` (3 more replies) 0 siblings, 4 replies; 5+ messages in thread From: jeremy.bennett at embecosm dot com @ 2023-09-11 18:21 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 Bug ID: 111375 Summary: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: jeremy.bennett at embecosm dot com Target Milestone: --- Created attachment 55878 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55878&action=edit Test case for the issue Found when building SPEC CPU 2017 621.wrf_s. The same problem appears to occur in 627.cam4_s and 628.pop2_s Reproducer (test.f90): MODULE a CONTAINS SUBROUTINE b(KTE) REAL,DIMENSION(KTE) :: c,e,f,q LOGICAL ae DO af=ag,ah DO i=ai,aj CALL ak(al,i,af,am,an,d,g,c,q,e,f,h,r & ,e,f,s,ao,LTOP,ap,aq,ar,as,at,au,av,aw & ,ae,ax,ay,az,ba,bb,bc & ,d,be,bf,bg,bh,bi,ai,aj,ag,ah,KTS,KTE) ENDDO ENDDO END SUBROUTINE b SUBROUTINE ak(al,i,af,am,an,bj,bk & ,bl,bm,bn,t,h,u,e,f,s,ao,LTOP,ap & ,aq,ar,as,at,au,av,aw,ae & ,ax,a,b,c,d,bc & ,bd,be,bf,bg,bh,bi,ai,aj,ag,ah,KTS,KTE) REAL,DIMENSION(:) :: bl,bm,bn,t REAL,DIMENSION(:) :: e,f REAL,DIMENSION(KTE) :: v LOGICAL ae l : DO j=1,w DO k=LTOP,m IF(o>=p)THEN n=x() ENDIF ENDDO y : DO z=1,2 DO k=LTOP,m aa=v(k)+aa ENDDO ab=aa DO k=KTS,m IF(k<=ac)ad=k ENDDO IF(LCOR<=ad)THEN DO k=LCOR,ad v=ab ENDDO ENDIF ENDDO y ENDDO l END SUBROUTINE ak END MODULE a Compile with: riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable test.f90 Output is: during RTL pass: vsetvl test.f90:14:18: 14 | END SUBROUTINE b | ^ internal compiler error: in get_avl_or_vl_reg, at config/riscv/riscv-vsetvl.cc:2297 0x98b1e3 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2297 0x98b1e3 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2271 0x15f8d27 insert_vsetvl /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:724 0x15f990d pass_vsetvl::commit_vsetvls() /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3615 0x15f9bc1 pass_vsetvl::pre_vsetvl() /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3728 0x15fa908 pass_vsetvl::lazy_vsetvl() /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4358 0x15faa11 pass_vsetvl::execute(function*) /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4393 0x15faa11 pass_vsetvl::execute(function*) /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4374 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. System information ================== Using built-in specs. COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper Target: riscv64-unknown-linux-gnu Configured with: /home/jeremy/gittrees/mustang/gcc/configure --target=riscv64-unknown-linux-gnu --prefix=/home/jeremy/gittrees/mustang/install --with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot --with-pkgversion=gf3ba57163ce --with-system-zlib --enable-shared --enable-tls --enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap --src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d --with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2 -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2 -mcmodel=medany' Thread model: posix Supported LTO compression algorithms: zlib gcc version 14.0.0 20230908 (experimental) (gf3ba57163ce) ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) 2023-09-11 18:21 [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) jeremy.bennett at embecosm dot com @ 2023-09-12 8:01 ` juzhe.zhong at rivai dot ai 2023-09-12 8:04 ` jeremy.bennett at embecosm dot com ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: juzhe.zhong at rivai dot ai @ 2023-09-12 8:01 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 JuzheZhong <juzhe.zhong at rivai dot ai> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |juzhe.zhong at rivai dot ai --- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> --- I can't reproduce the ICE in your testcase with same command. ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/install/bin/riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable bug.f90 No ICE. Could you help me with that ? ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) 2023-09-11 18:21 [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) jeremy.bennett at embecosm dot com 2023-09-12 8:01 ` [Bug middle-end/111375] " juzhe.zhong at rivai dot ai @ 2023-09-12 8:04 ` jeremy.bennett at embecosm dot com 2023-09-12 8:07 ` juzhe.zhong at rivai dot ai 2023-09-12 16:22 ` jeremy.bennett at embecosm dot com 3 siblings, 0 replies; 5+ messages in thread From: jeremy.bennett at embecosm dot com @ 2023-09-12 8:04 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 --- Comment #2 from Jeremy Bennett <jeremy.bennett at embecosm dot com> --- (In reply to JuzheZhong from comment #1) > I can't reproduce the ICE in your testcase with same command. > > ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/ > install/bin/riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d > -c -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable bug.f90 > > > No ICE. > > Could you help me with that ? Hi JuzheZhong I built with the following components: Repository SHA-1 hash (commit ID) ---------- ---------------------- gcc 316d57da5bb9205b946afc56d78582fee874e4b5 binutils-gdb 9a343d2bb57c4555dedad9b43907aeeda7b51dae glibc 073edbdfabaad4786e974a451efe4b6b3f7a5a61 Is this the same as you? I'll do a clean rebuild with the latest tool chain in case this problem has been fixed. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) 2023-09-11 18:21 [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) jeremy.bennett at embecosm dot com 2023-09-12 8:01 ` [Bug middle-end/111375] " juzhe.zhong at rivai dot ai 2023-09-12 8:04 ` jeremy.bennett at embecosm dot com @ 2023-09-12 8:07 ` juzhe.zhong at rivai dot ai 2023-09-12 16:22 ` jeremy.bennett at embecosm dot com 3 siblings, 0 replies; 5+ messages in thread From: juzhe.zhong at rivai dot ai @ 2023-09-12 8:07 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 --- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> --- (In reply to Jeremy Bennett from comment #2) > (In reply to JuzheZhong from comment #1) > > I can't reproduce the ICE in your testcase with same command. > > > > ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/ > > install/bin/riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d > > -c -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable bug.f90 > > > > > > No ICE. > > > > Could you help me with that ? > > Hi JuzheZhong > > I built with the following components: > > Repository SHA-1 hash (commit ID) > ---------- ---------------------- > gcc 316d57da5bb9205b946afc56d78582fee874e4b5 > binutils-gdb 9a343d2bb57c4555dedad9b43907aeeda7b51dae > glibc 073edbdfabaad4786e974a451efe4b6b3f7a5a61 > > Is this the same as you? I'll do a clean rebuild with the latest tool chain > in case this problem has been fixed. Current GCC enable scalable vectorization by default now. I think you could try again with the latest GCC. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) 2023-09-11 18:21 [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) jeremy.bennett at embecosm dot com ` (2 preceding siblings ...) 2023-09-12 8:07 ` juzhe.zhong at rivai dot ai @ 2023-09-12 16:22 ` jeremy.bennett at embecosm dot com 3 siblings, 0 replies; 5+ messages in thread From: jeremy.bennett at embecosm dot com @ 2023-09-12 16:22 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375 Jeremy Bennett <jeremy.bennett at embecosm dot com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #4 from Jeremy Bennett <jeremy.bennett at embecosm dot com> --- Thanks @JuzheZhong, I have tried again with the latest GCC and the problem has gone away. This can now be marked as fixed. ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-09-12 16:22 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-09-11 18:21 [Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass) jeremy.bennett at embecosm dot com 2023-09-12 8:01 ` [Bug middle-end/111375] " juzhe.zhong at rivai dot ai 2023-09-12 8:04 ` jeremy.bennett at embecosm dot com 2023-09-12 8:07 ` juzhe.zhong at rivai dot ai 2023-09-12 16:22 ` jeremy.bennett at embecosm dot com
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