From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 32A2138708E1; Sat, 15 Jun 2024 08:35:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32A2138708E1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1718440544; bh=savF13nlfmle2TuNFn2swOVob1HLjTxPoAaMpzsIsIY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=dn7uYr0v7z5pp+Rjfy0g77b25rFMphrbStUzXyOImFyDZVaawKPCzIxeOsT31vMC5 2mivCoRtTs4mTRvG/MfRnmf/SUoa7fTWX0DfQGGXeuhnbKsb0ZXcyuuBSu9s7Tkzvq 2mlKCoQIKl4VIFXWmpvDoVCpJ6X0Jdy0RdEo3j+I= From: "lis8215 at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/111376] missed optimization of one bit test on MIPS32r1 Date: Sat, 15 Jun 2024 08:35:43 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: unknown X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: lis8215 at gmail dot com X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: INVALID X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: syq at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111376 --- Comment #16 from Siarhei Volkau --- Might it be that LoongArch have register reuse dependency? I observed similar behavior on XBurst with load/store/reuse pattern: e.g. this code LW $v0, 0($t1) # Xburst load latency is 4 but it has bypass=20 SW $v0, 0($t2) # to subsequent store operation, thus no stall here ADD $v0, $t1, $t2 # but it stalls here, because of register reuse # until LW op is not completed.=